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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 4
24
3-D TECHNOLOGY:
FAILURE ANALYSIS CHALLENGES
Ingrid De Wolf, imec and KU Leuven
ingrid.dewolf@imec.beEDFAAO (2016) 4:24-29
1537-0755/$19.00 ©ASM International
®
INTRODUCTION
Chip-level three-dimensional integration, that is, 3-D
stacked IC (3-D SIC), where chips are thinned, stacked on
each other, and vertically interconnected using through-
silicon vias (TSVs) and microbumps, promises a large
improvement in performance and functionality of micro-
electronics systems. However, it also promises additional
challenges for the failure analysis (FA) community.
Two-dimensional chip-level FA already must deal
with the challenges imposed by the high density, which
reduces dimensions and increases complexityof theactive
devices, together with an increased number of layers in
the back-end-of-line (BEOL) required to interconnect it
all. The main FA solutions approach the problem from
the backside of the chip, requiring appropriate thinning
and probing solutions. One could happily argue that life
will become easier in 3-D, because the chips are already
thinned before stacking, thus reducing that barrier. This
may partly be the case; however, the current 3-D chips are
only thinned to typically 50 µm, which is not enough for
backside probing of high-density, nanosized transistors.
In addition, they are stacked rather rigidly on top of each
other. Even when a failure location is electrically found to
be restricted to a particular chip, removing one chip from
a stack without damaging it is certainly an issue that will
bring new challenges for sample-preparation specialists.
In addition, the chips are electrically interconnected in a
vertical manner. A failuremay be somewhere on the chip,
but it may also be in the interconnection between the
chips, in the TSVs inside the chips, or in the microbumps.
Misalignment easily leads to bad interconnections and
potential failures. Breakdown of the TSV liner can cause
leakage paths and copper diffusion into the silicon.
Intermetallic formation can cause issues in the micro-
bumps. Stress in the TSV can affect nearby transistors
or cause damage in the BEOL layers on top. In addition
to these new interconnection elements, mechanical and
thermal issues will also bring additional risks for failure,
especially if mechanically fragile ultra-low-k dielectrics
are used in the BEOL. There is a clear need for techniques
that can nondestructively locate a failure in a (packaged)
3-D stack, togetherwith sample-preparationmethods that
allow easy and fast access to the failure site for further
inspection.
Referring to FA for 2-D chips, Dave Vallett mentioned
in the October 1997
IEEE Spectrum
that “FA is sometimes
rightly compared to looking for aneedle inahay stack, and
in this case, the haystack is getting larger, while the needle
is getting smaller.” This is still true, but when talking about
3-D IC technology, one could modify his quote to: “3-D FA
is like looking for a needle in a hay barn, with the needle
getting smaller and the hay barn getting ever bigger, and
an increasing amount of cats and mice messing things
up,”with the “cats andmice” being TSVs andmicrobumps.
X-RAY IMAGING AND SCANNING
ACOUSTIC MICROSCOPY
The most common nondestructive techniques that
allow a look inside a 3-D stack of chips are x-ray imaging
and scanning acoustic microscopy (SAM). These tech-
niques are well known from package-level FA. Their
main drawback for 3-D applications has been their
“THERE IS A CLEAR NEED
FOR TECHNIQUES THAT CAN
NONDESTRUCTIVELY LOCATE A FAILURE
IN A (PACKAGED) 3-D STACK, TOGETHER
WITH SAMPLE-PREPARATION METHODS
THAT ALLOW EASY AND FAST ACCESS
TO THE FAILURE SITE FOR FURTHER
INSPECTION. ”