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A D V A N C E D M A T E R I A L S & P R O C E S S E S | F E B R U A R Y 2 0 1 6
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USINGHIGHRESOLUTION
S/TEMTOANALYZE
SMARTPHONE DISPLAYS
The rapidly increasing complexity of microelectronic devices is necessitating
the use of sophisticated imaging tools to analyze and correct defects.
W
ith more than 60 research
institutions, Fraunhofer is
Europe’s largest application-
oriented research organization. Among
these units is the Fraunhofer Institute
for Microstructure of Materials and Sys-
tems IMWS, which includes the Fraun-
hofer Center for Applied Microstruc-
ture Diagnostics (CAM). Its specialized
“microstructure of materials and sys-
tems” approach identifies weaknesses
and defects in materials and compo-
nents, determines their causes, and
then develops safer components, new
materials, and better manufacturing
processes.
Researchers analyze nano and mi-
crostructures, determine material and
component properties, and simulate ap-
plication behavior using material mod-
els. Activities focus on detecting, analyz-
ing, andpreventing electrical, electronic,
and mechanical defects and failures
during development, design, and field
application. Together with equipment
suppliers, the CAM unit also develops
tools for diagnostics and testing that en-
able improved detection and control of
defects and faults via industrial failure
analysis and quality monitoring.
Fraunhofer CAM specializes in
process and material assessment and
physical failure analysis for semicon-
ductor technologies, packaging, as-
sembly, system integration, and MEMS
components. Its research includes
preparation techniques based on fo-
cused ion beams and lasers that im-
prove throughput and capability in
industrial failure diagnostics and nano-
analytics. The center offers a wide ar-
ray of analytical capabilities, including
nondestructive defect localization, FIB
and electron microscopy, surface and
trace analysis, crystallography and op-
tical spectrometry, surface topography
and deformation, polymer characteri-
zation, mechanical and reliability test-
ing and modeling, and electrochemical
characterization and corrosion testing.
TEM SAMPLE PREPARATION
Among the most challenging tasks
in today’s microelectronics industry is
preparation of ultra-thin, site-specific
samples for examination in a TEM instru-
ment. TEM, and its close relative STEM,
offer sub-angstrom (sub 0.1 nm) reso-
lution, good enough to resolve individ-
ual atoms in many electronic materials.
Their use in semiconductor manufactur-
ing has grown rapidly in recent years as
the size of critical features has shrunk be-
yond the resolving power of SEMs (~1.0
nm), which have long been the mainstay
of the industry for failure analysis and de-
fect characterization. Samples for S/TEM
must be thin enough to transmit elec-
trons—generally less than 100 nm, and
thinner is almost always better. Formany
purposes, they also need to be thinner
than the structure being examined. A
transistor gate that is 22 nm long requires
a lamella that is 22 nm or less in thick-
ness to provide an unambiguous cross-
sectional view.
Finally, as modern devices have
moved away from conventional planar
designs to complex 3D architectures
(e.g., FinFETs), the cross section must
also be accurately oriented to the de-
vice. Accurate sample preparation is
essential because these defects are
relatively rare but contain important
information about the manufacturing
process. They are expensive to obtain
and if they are destroyed in the prepa-
ration process the information is lost
forever. Dual beam instruments, which
in a single instrument combine a SEM
for high-resolution imaging and a FIB
for removing (and occasionally adding)
material to the sample with nanometer
scale precision, are the only reliable
and efficient way to meet these sample
requirements.
In dual beam based sample prepa-
ration, the targeted defect is first lo-
cated using information provided by
defect inspection or electronic test
procedures. This may involve navigat-
ing to the physical location of a device
identified by its logical location us-
ing coordinates provided by the CAD
design layout. At the target location,
packaging material and overlaying cir-
cuit layers must be removed. The FIB
is then used to mill away material on
either side of a thin lamella containing
the target. The lamella is cut free from
the wafer, then extracted and attached
to a TEM sample grid. Next, the FIB is
used again to thin the lamella to the
desired final thickness, ready for exam-
ination in the TEM. One company that
has made great progress in automat-
ing the sample preparation process is