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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 4

microscopy face challenges to identify the correct defect

area with the sample still fully functional. In addition,

sample-preparation techniques such asmechanical cross

sectioning and top-down sample delayering are reaching

their limitationswhere preparation artifacts can no longer

be neglected.

ANALYSIS OF CURRENT PACKAGE

FA FLOWS, CHALLENGES, AND

REQUIREMENTS

While complex packaging is desired from a product

point of view, it also induces additional risks and challeng-

es regarding manufacturing yield, device performance,

and life-time reliability. Considering these facts, a new

threshold of requirements for successful FA is introduced:

• Using copper as the main material for TSVs and

micropillar realization induces a coefficient of thermal

expansion (CTE) mismatch to silicon material. As a

result, thermal and mechanical tension can lead to

crack introduction.

FA request:

Sample preparation is requested to avoid

smearing effects during mechanical cross sectioning.

• Using thinned-die technology (e.g., interposer), espe-

cially on large package products, raises the influence

of warpage and die-bowing effects. Similar to CTE

mismatches, these can introduce crack propagation

and layer delamination.

FA request:

Handling of thin but large sample sizes;

compensation for stress relaxation during sample

deprocessing.

• Shrinking interconnect dimensions lead to a require-

ment to lower critical void size and concentration.

FA request:

Artifact-free sample preparation and

cross sectioning; early failure detection with shrinking

defect size.

Analyzing these requirements, the need to maintain

overall device functionality and therefore nondestructive

testingand fault isolationbecomesapriority. Furthermore,

after successful defect isolation, a precise and local target-

preparation method is desired that allows root-cause

imaging in any layer inside the package stack. Although

these requirements are not fully new to the FA industry,

current state-of-the-art methods face their physical

limitations:

• Optical-based methods, such as photon emission

microscopy, optical beam-induced resistance change,

or laser scanning microscopy, are often used for fault

isolation but face limitations due to the complex

package setups that block optical access for fully pack-

aged devices.

• Confocal scanning acoustic microscopy is often used

for delamination or crack detection within package

products. However, due to the increasing layer and

material amount combined with shrinking intercon-

nect size, early defect detection becomes more and

more difficult.

• Time-domain reflectometry is capable of isolating spe-

cifically the defect depthwithin the package. However,

due to its pulse length in the megahertz range, it

cannot keep up with the shrinking interconnect size; a

z

-resolution limit is increasingly hindering successful

defect isolation.

• Mechanical cross sectioning is a state-of-the-art, fast,

and effective way to achieve root-cause analysis.

Within the introduction of copper-based interconnects

and shrinking feature size, a shift toward focused ion

beam (FIB) techniques is recognizable. As for package

FA, standard FIB tools suffer from inadequate beam

currents, which results in long cross-sectioning times

in the tens-of-hours range.

EMERGING PACKAGE FA METHODS FOR

2-D/2.5-D/3-D PRODUCT ANALYSIS

To overcome the limitations mentioned in this article

and to meet FA requirements, several techniques have

been either further or newly developed:

• Lock-in thermography

(LIT) is a thermal defect localiza-

tionmethod that canbe applied for short localization in

3-D. Its resolution and sensitivity aswell as the capabil-

ity to isolate defectswithin specific 2.5-D/3-Dpackages

havebeensuccessfullydemonstratedandpublished.

[4,5]

• Superconducting quantum interference device (SQUID)

or magnetic current imaging

has been further devel-

oped to isolate both shorts and opens and has been

an often-applied board-level FA tool. Current devel-

opments aim to adapt this concept toward CSP-sized

samples.

[6]

• 3-D x-ray

has been widely adapted for semiconductor

needs, and it provides high resolution and sensitivity.

With the optimizationof sources anddetectormaterial,

a significant decrease in measurement time has been

noticed. 3-D x-ray microscopy (XRM) offers a solution

for structural analysis in complex 3-D integrated circuits

because it can nondestructively penetrate through

stacked materials and visualize internal structures

with high resolution, even for intact 200 and 300 mm

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