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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 4

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2. F. Beaudoin, S. Lucarini, F. Towler, S. Wu, Z. Song, D. Albert, L. Safran,

J. Sylvestri, G. Karve, X. Yu, E. Kachir, and N. Jungmann: “Challenges

and Benefits of Product-Like SRAM in Technology Development,”

Proc. Int. Symp. Test. Fail. Anal. (ISTFA),

2011, p. 362.

3. A. Deyine, P. Perdu, K. Sanchez, and J.C. Courrège: “Dynamic Power

Analysis under Laser Stimulation: A New Dynamic Laser Simulation

Approach,”

Proc. Int. Symp. Test. Fail. Anal. (ISTFA),

2010, p. 217.

4. E. Barbian, G. Crow, W.T. Swe, and M.C. Phillips: “Practical

Implementation of Soft Defect Localization (SDL) in Mixed Signal

and Analog ICs,”

Proc. Int. Symp. Test. Fail. Anal. (ISTFA),

2011, p. 158.

5. R. Guo and S. Venkataraman: “A Technique for Fault Diagnosis of

Defects in Scan Chains,”

Proc. Int. Test Conf. (ITC),

2001, p. 268.

6. Z. Song, S.P. Neo, T. Tun, C.K. Oh, and K.F. Lo: “Diagnosis and Failure

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Circuits (IPFA),

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7. Y.S. Ng, T. Lundquist, D. Skvortsov, J. Liao, S. Kasapi, and H. Marks:

“Laser Voltage Imaging: ANewPerspective of Laser Voltage Probing,”

Int. Symp. Test. Fail. Anal. (ISTFA),

2010.

8. Y.S. Ng, H. Marks, C. Nemirov, C.C. Tsao, and J. Vickers: “Scan-Shift

Debug Using LVI Phase Mapping,”

Int. Symp. Test. Fail. Anal. (ISTFA),

2013.

9. T. Parrassin, G. Celi, S. Dudit, M. Vallet, A. Reverdy, P. Perdu, and

D. Lewis: “Laser Voltage Imaging and Its Derivatives, Efficient

Techniques to Address Defect on 28 nmTechnology,”

Int. Symp. Test.

Fail. Anal. (ISTFA),

2013.

10. H.K. Heinrich, D.M. Bloom, B.R. Hemenway, K. McGroddy, and U.

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IEEE Trans. Electron Dev.,

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(11), p. 1860.

11. M. Paniccia, T. Eiles, V.R.M. Rao, andW.M. Yee: “Novel Optical Probing

Technique for Flip-Chip Packaged Microprocessors,”

Proc. Int. Test

Conf. (ITC),

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12. Y.S. Ng, W. Lo, and K. Wilsher: “Next Generation Laser Voltage

Probing,”

Proc. Int. Symp. Test. Fail. Anal. (ISTFA),

2008, p. 249.

13. S. Kolachina: “Introduction to Laser Voltage Probing (LVP) of

Integrated Circuits,”

Microelectronics Failure Analysis Desk Reference,

6th ed., ASM International, 2011.

14. Z.G. Song, F. Beaudoin, S. Lucarini, S. Wu, Y.Y. Wang, L. Arie, and K.

Steiner: “Logic Yield Learning Vehicle Failure Analysis in Technology

Development,”

Proc. Int. Symp. Test. Fail. Anal. (ISTFA),

2012, p. 520.

ABOUT THE AUTHORS

Zhigang Song

has 19 years of experience in electronic device failure analysis. He has worked at

AMD, Chartered Semiconductor Manufacturing Limited, theMicroelectronics Division of IBM, and cur-

rently works in the failure analysis lab at Globalfoundries, East Fishkill, NY, as a Principal Member of

the Technical Staff. During his failure analysis career, Dr. Song has led failure analysis teams for SRAM

and logic device failure analysis to support advanced silicon-on-insulator and bulk semiconductor

process technology development for the latest several consecutive generations. Dr. Song received

a Bachelor of Science degree from Fudan University, China, in 1988; a Master of Engineering from

Beijing Institute of Chemical Technology, China, in 1990; and a Ph.D. from the National University of

Singapore in 1998. He has published more than 50 papers in journals and at conferences and holds several U.S. patents.

He is also an active ISTFA contributor and participant.

Laura Safran

is currently a diagnostics engineer at Globalfoundries’ Advanced Technology

Development Diagnostics Lab in East Fishkill, NY.  During her extensive career in semiconductor

diagnostics and physical failure analysis, she has supported teams in both manufacturing and

development within IBM, Philips Semiconductor, and NXP. Laura holds a Bachelor of Science degree

in materials science from Michigan State University.

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