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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 3

TAKE A CLOSER LOOK AT ELECTRICALLY-ENHANCED

LADA: SETUP

S.H. Goh, B.L. Yeoh, G.F. You, Y.H. Chan, Zhao Lin, and Jeffrey Lam

Globalfoundries, Technology Development, Product/Test and Yield Engineering, Singapore

and

C.M. Chua, Semicaps Pte Ltd., Singapore

SzuHuat.Goh@globalfoundries.com

INTRODUCTION

On sub-28 nm process technology, silicon patterning

conformance to design, especially front-end-of-line, has

run up against the limits of physics, bringing about a para-

digm shift from defect-limited hard failures to increasing

occurrences of design-margin soft failures as a result of

the shrinking process window. Therefore, the role of soft

defect localization (SDL) techniques in yield engineering

has become more important. It is common to speak of

SDL and laser-assisteddevice alteration (LADA) when such

failures need to be investigated.

LADA uses a continuous-wave 1064 nm photo-

current-inducing laser to temporarily alter transistor

characteristics through the silicon substrate. The outcome

is a flip in the tester pass-fail state. The position of the

scanning laser is correlated to the state transition and reg-

istered for signal image acquisition.

[1]

Such an approach is

well known to be effective for localization of speed path

degradation

[2]

and subtle process defects.

[3]

The applica-

tion of LADA extends beyond such spatial localizationwith

the innovation of time-resolved LADA (TR-LADA), which is

capable of extracting temporal information from the fail-

ures by using a 1064 nm pulsed laser to “probe” different

test cycles in each test loop.

[4]

It offers new insights, such

as failure mode identification

[5]

and knowledge of propa-

gation delays.

[6]

In some cases, an improved LADA signal

spatial resolution has also been observed.

[7]

The current

state-of-the-art inTR-LADA is basedon a 50 ps pulse-width

laser that enables the interrogation on a single test cycle.

As a matter of fact, both LADA and TR-LADA signals can

be attributed to either potential sites of existing issues or

devices with low threshold to laser stimulation, the latter

also known as artifacts. There is no means to intuitively

differentiate between the two by merely monitoring the

transition of test pass-fail states. This is the main moti-

vation behind the innovation of electrically-enhanced

LADA (EeLADA).

[8,9]

It works by the concept of eliminating

these artifacts by extracting fail information fromall LADA

events in terms of failing pins/cycles and comparing them

against the actual fail information derived from testing

the bad unit.

[7]

In this way, only the LADA signals relevant

to the actual failure will be displayed. This methodology

also presents an advancement that overcomes LADA’s

traditional limitation on soft failures and creates newpos-

sibilities for hard failure defect localization. The concept

of EeLADA can be realized in a number of ways, and two

such approaches will be discussed.

WHAT IS ELECTRICALLY-ENHANCED

LADA?

Figure 1 shows a block diagram illustrating the EeLADA

concept. In general, although the setup refers to a wafer-

level configuration, it applies to package level as well.

Unlike a typical synchronous LADA setupwhere the tester

generates a trigger in the event of a flip in the test state,

EeLADA integrates an additional comparator module to

determine the trigger pulse generation. The integrated

circuit (IC) device under test is activated by the tester,

which refers to the test pattern for the biasing conditions.

A test pattern is defined by a three-dimensional matrix

of test vectors that correspond to specific pin names and

cycle numbers. The test vectors may represent inputs or

outputs. Inputs serve as driving signals into the IC, and

outputs, also called compare test vectors, provide the

expected states to determine a test pass-fail.

Prior to debug on EeLADA, the bad IC is tested, and

a standard failure log containing details of the compare

fail vectors and the respective fail pin/cycles is obtained.

This is referred to as the reference failure log, as shown

in Fig. 1, and is called the reference failure signature. The

comparatormodule receives this fail log and commits it to

memory. As the tester activates the soft failing IC and the

EDFAAO (2016) 3:10-16