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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 3
in Fig. 9(b), because laser stimulations at these locations
do not result in a fail. This is the effect of masking the
compare vectors.
Another experiment was performed by creating a
programmed defect in the active area of some random
logic using a 1340 nm wavelength laser through the
silicon substrate. The device is tested, and the fail log is
collected. Figure 10(a) shows the EeLADA overlay image
for the case of inverting only the first fail cycle of the
failure signature, and Fig. 10(b) shows the case of invert-
ing the last fail cycle on the technical pattern. It should be
remembered that EeLADA is performed on a passing IC.
The black dot denotes the exact programmed defect loca-
tion. The arrows pinpoint the EeLADA signals. It is evident
that although the signal does not precisely coincide with
the defect, the observation within the vicinity of 10 µm is
sufficient to guide and achieve physical failure analysis
success on the bad die. The results from this experiment
demonstrate the potential of employing EeLADA for hard
defect localization. More comprehensive studies are nec-
essary in this aspect.
HARDWARE VERSUS SOFTWARE
APPROACH
While both hardware and software approaches are
able to realize the concept of filtering LADA signals, it is
worth highlighting again that the manner of operation is
significantly different. The lattermethod is not as straight-
forward, but the outcome is congruent, as evidenced
earlier. The idea of matching is more intuitive by using
the comparator circuit. For EeLADA inspection time, the
hardware approach has a slight advantage, because the
dwell time per pixel is shorter since it is no longer neces-
sary to incorporate wait times for the accommodation of
synchronizing and pass/fail pulses in a single test loop.
However, the flipside in thismethod lies in the use of cables
that may not be suited for IC testing speeds above 50MHz.
CONCLUSION
Whenever a LADA event occurs due to a state transi-
tion from fail to pass, the signal relevance to the exact
failing signature is obvious. However, the reverse is not
true. Therefore, signals that arise froma pass-to-fail state
transitionaremore concerning. Normally, they can involve
various combinations in terms of failingpins and cycles, be
it conventional LADA or TR-LADA. EeLADA is an evolution
that resolves this ambiguity to extract relevant signals for
analysis. The fundamentals behind EeLADA have been
detailed in this article. Although EeLADA appears to be a
derivative of LADA, in practice, EeSDL will work as well. As
a final takeaway, it isworth amoment topause and review
the custom way IC failures are debugged. Should defect
localization always be performed directly on failed dice?
The preliminary demonstration of the EeLADA application
to hard defect localization is an exemplary example of
deviating from this rule of thumb.
REFERENCES
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ABOUT THE AUTHORS
S.H. Goh
received his B.Eng, and Ph.D. degrees in electrical and computer engineering from the
National University of Singapore. His doctorate research on simulation and implementation of the
aplanatic refractive solid immersion lens was awarded a conference Best Paper and was part of a
team project that received the 2009 Singapore President’s Technology Award. Dr. Goh is currently
with Globalfoundries, Product, Test, and Failure Analysis Division, Singapore, where he leads a team
responsible for product failure diagnostics and advanced methodologies to accelerate yield ramp.
His main focus is on development of dynamic fault isolation techniques, wafer-level fault isolation
methods, and leveraging cross-functional domain knowledge of design, test, and failure analysis to
enhance yield learning. His work has been published in conference proceedings and journals. Dr. Goh is also an active
contributor to IPFA and ISTFA technical committees.