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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 1
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ABOUT THE AUTHOR
YannWeber receivedhisM.S. degree in electrical engineering in 2004 fromPolytechnicOrsay France
and his second M.S. degree in nanostructures and microsystems for electronics from Paris Sud Orsay
University the same year. He started his professional career by completing a Ph.D. under the public
laboratory collaboration of Freescale and the Laboratory for Analysis and Architecture of Systems/
FrenchNational Center for Scientific Research at Toulouse, where he developed alternative structures
in semiconductor power VDMOS devices to increase breakdown voltage and on resistance. He gradu-
ated in 2008 and received honorific distinction from the “Académie des Chiffres et Belles Lettres” of
Toulouse for his high quality of scientific contribution. Dr. Weber then joined the Quality Department of Freescale and
worked for five years as an FA engineer. Since 2013, he has been a technology and reliability engineer responsible for
leading all extrinsic reliability stresses for Freescale’s newanalog and sensor technologies. He has authored or co-authored
many articles and was recognized with the Best Paper award at the ESREF 2013 conference.
FIB/SEMWORKSHOP
The ninth annual FIB/SEM Workshop will be held on Thursday, February 25, 2016, at the Kossiakoff Center at Johns
Hopkins Applied Physics Laboratory in Laurel, Md. It features a full day of presentations and posters by FIB users and
vendors highlighting interesting new FIB applications and the latest technology. As always, there will be plenty of oppor-
tunities for informal discussion of new techniques and applications as well as time for (re)connecting with fellow FIBers.
There is no fee to attend the meeting, and breakfast and lunch are provided. Registration deadline is February 19.
For more information, visit .
NOTEWORTHY NEWS
4. W. Han: “Introduction to Scanning Microwave Microscopy
Application,” Agilent Application Note, June 16, 2008.
5. M.A. Fenner, F. Kienberger, H. Tanbakuchi, H.-P. Huber, and P.
Hinterdorfer: “Quantitative Measurement of Electric Properties
on the Nanometer Scale Using Atomic Force Microscopy,” IEEE
Semiconductor Conference Dresden (SCD), 2011, pp. 1-4.
6. S. Alves, P. Rousseille, and T. Zirilli: “Fault Localization of Metal
Defects with Si-CCD Camera in Analog Device Functional Failure,”
Proc. 33rd Int. Symp. Test. Fail. Anal. (ISTFA), Nov. 2013 (San Jose,
CA), pp. 398-402.
7. M.M. El-Gomati, T.C.R. Wells, I. Müllerová, L. Frank, andH. Jayakody:
“Why Is It That Differently Doped Regions in Semiconductors Are
Visible in Low Voltage SEM?” IEEE Trans. Electron Dev., Feb. 2004,
51(2), pp. 288-92.
8. M.W. Jenkins: “ANewPreferential Etch for Defects inSiliconCrystals,”
J. Electrochem. Soc., 1977, 124, pp. 757-59.
9. W.F. Lee, A. Chin, and P.H. Seah: “Application of Wright Etch in Failure
Analysis onLocalizedAbnormal Implant Profile inWafer Fabrication,”
Int. Symp. Phys. Fail. Anal. Integ. Circuits (IPFA),2011, pp. 1-4.
10. J.G. Van Hasell and X.-M. Zhang: “Process Induced Defects in the
Silicon Substrate: Approaches for Successful Failure Analysis,”Proc.
Int. Symp. Test. Fail. Anal. (ISTFA),Nov. 2010 (Dallas, TX), pp. 92-97.
11. G.K. Su, D. Jin, S.-R. Kim, T.-H. Chan, H. Balan, Y.-T. Lin, K.-J., Han,
and S. Hsia, “Pipeline Defects in Flash Devices Associated with Ring
OSF,” Semicond. Manuf., 2003, p. 144.
12. C.T. Wang, H. Hadaad, P. Berndt, B.-S. Yeh, and B. Connors: “Pipeline
Defects inCMOSDevices Causedby SWAMI Isolation,”IEEE Int. Reliab.
Phys. Symp. (IRPS), 1992, pp. 85-90.