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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 1
ISTFA 2016 SAMPLE-PREP/
3-D PACKAGE-PREP USER GROUP
Moderators: Nathan Bakken, Intel Corporation, and Roger Stierman, RJ Stierman Consulting
The Sample-Prep User Group hosted four technical
presentations toward the development of new
capabilities in the laboratory. The first presentation
discussed scaling up focused ion beam (FIB) techniques
to enable processes that would typically involve incom-
patible materials systems or excessive processing time.
The next two presentations addressed methods to scale
down existing mechanical and optical deprocessing
techniques tomeet new tolerance requirements. The final
presentation described some fundamental changes in the
backside silicon thermal models used to describe systems
with remaining silicon thickness (RST) approaching zero.
The session was concluded by an interactive discussion
where the audience engaged with the panel of User
Group authors. More than 85 people attended the Sample
Prep/3-D User Group meeting, which was sponsored by
Varioscale, Inc.
“Novel Sample Preparation Techniques for
Semiconductor Process Technology Development and
Advanced Packaging Analysis Using Plasma FIB” was
presentedby SurendraMadala of Thermo Fisher Scientific
(FEI group). The presentation noted the issues with con-
ventional FIB processing: extremely long time and excess
heat generation for large areas and volumes, and depth
of disturbed layers versus the shrinking features’ sizes.
Plasma FIB examples showing less damage and feature
retention in reasonable timeswere shown for applications
with dimensions up to many hundreds of microns.
“Using Microline Indentation to Precisely Downsize
<100-µm-Thin Die out of the Package” was presented by
Janet Teshima of LatticeGear. The difficulty of reaching a
thin die’s failure site was noted, especially die extracted
froma package. The use of sacrificial silicon pieces, along
with amicrospot mechanical cleaving fixture, was shown
to produce results with high yields. It was reinforced
during the discussion session that the simple technique
ISTFA '16 USER GROUP SUMMARIES
achieved high success rates. It was also noted that align-
ment accuracy depended on the alignment optics and
could potentially continue to be scaled with the right
microscope and/or reduction of the 10 µm diamond
cleaving apex.
“Pulsed Laser Preparation of Uniform, Submicrometer
Remaining Silicon over Active Circuits” was presented by
Scott Silverman of Varioscale, Inc. A strategy to overcome
the current uniform material-removal rate in a defined
machining area by selectively blanking laser pulses was
shown to enable contoured laser-assisted chemical-
etched (LACE) surfaces. The ability to shape the etched
surface was proposed to enable improved trench toler-
ances in addition to other capabilities. During the panel
discussions, the minimum RST achievable by LACE as
limited by circuit invasiveness in addition to machining
accuracy was discussed. The author presented some
theory to support paths to tens-of-nanometer RST with
circuit invasiveness limited by careful control of the melt
depth andaverage incident laser power, including prelimi-
nary results for ultraviolet 355 nm pulsed-laser sources.
“Submicron Prep Impact on Silicon Lateral Heat
Dissipation, Junction Temperature, and FinFET Validation
Thermal Management”was presentedby Vladimir Vlasyuk
of Intel. This presentation considered the heat diffusion
from optical probing on devices thinned to sub-3-µm
silicon. Air cooling was considered suboptimal; a liquid
cooling solution provided better results. During the dis-
cussion session, the audience noted quite fervently that
challenges facing sample prep are rapidly shifting from
surface quality andmachining acuity toward overcoming
thermal and mechanical barriers. The author proposed
that additional workwill be required for thermal manage-
ment of very thin silicon device preparation.
The session was closed several minutes after the
scheduled conclusion, with conversations continuing