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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 2
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visible after passivation removal. Even though the defects
were clearly visible, their cause, extent, and implications
were unknown. Extensive study over several years was
required to understand the physics of stress-induced
voiding. Because of quantummechanical tunneling, lines
with stress voiding may operate even at low frequencies.
However, the voids become wider very slowly with time
and eventually cause low-frequency failure. Heating and
cooling can alter the failure signature and make it harder
to identify. Removal of the passivation or other encap-
sulating layers will change stress cracks, usually making
them worse. The analyst then must answer the question
of whether the identified defects were present before
deprocessing or are a result of deprocessing.
Today, it is understood that different CTEs ofmetal and
surrounding oxide produce stress that induces voiding.
Stress voids are a fact that must be expected. Barrier
metals have been added to provide a redundant path
around a void in a long metal strip. A void in a long metal
strip no longer causes an electrical failure. Stress void
failures are not that easily eliminated. Vias, or connec-
tions between layers of conductors, are locations where a
stress void can produce an electrical open. For aluminum
systems, tungsten plugs can create stress and introduce
open possibilities.[6] For copper systems, vias again offer
unique possibilities of failure.[7] Redundant vias may be
used to avoid IC failure despite possible voiding. However,
redundant vias may not always be possible.
In today’s ICs,many newdiagnostic techniquesmay be
required to electrically define a defect site. If the defect is
in themetallization, stress cracks become a consideration.
There will not be one dramatic finding that proves stress
voiding as the cause. If the defect is a stress void, it will not
be the only one; other voidswill exist in different or similar
places. Metal purity may be an issue. The analyst will be
challenged tofindandanswer goodquestions that hone in
on the cause. When peripheral symptoms are verified and
other mechanisms have been eliminated, stress voiding
will top the list. It will be up to the analyst or responsible
colleagues to finalize the conclusion. The procedure may
not be that different from1980, whichmay be why failure
analysis is still so much fun.
REFERENCES
1. J. Klema, R. Pyle, and E. Domangue: “Reliability Implications of
Nitrogen Contamination during Deposition of Sputtered Aluminum/
Silicon Metal Film,”Int. Reliab. Phys. Symp. (IRPS), 1984, pp. 1-5.
2. J. Yue, W. Funston, andH. Taylor: “Stress-Induced Voids in Aluminum
Interconnects during Processing,” Int. Reliab. Phys. Symp. (IRPS),
1985, pp. 126-37.
3. W. Filter: “Stress Voiding in IC Interconnects—Rules of Evidence for
Failure Analysts (Part I),”Electron. Dev. Fail. Anal., Nov. 1999, 1(4),
pp. 21-23.
4. D.G. Robinson: “Quantifying the Impact of Materials Degradation on
Storage Reliability: Stress Voiding of Integrated Circuits,” PMC2000-
212, Eighth ASCE Specialty Conference on Probabilistic Mechanics
and Structural Reliability, 2000.
5. T. Turner and B. Root: “The Influence of Stress on Aluminum
Conductor Life,” Int. Reliab. Phys. Symp. (IRPS), 1985, pp. 142-47.
6. S. Domae, H. Masuda, K. Taatiwa, Y. Kato, and M. Fujimoto: “Stress-
Induced Voiding in Stacked Tungsten Via Structures,” Int. Reliab.
Phys. Symp. (IRPS), 1998, pp. 318-22.
7. H.W. Yao, P. Justison, and J. Poppe: “Stress-Induced Voiding Risk
Factor and Stress Migration Model for Cu Interconnect Reliability,”
Int. Reliab. Phys. Symp. (IRPS), 2013, pp. 2C.5.1- 5.8.
ABOUT THE AUTHOR
David Burgess is a failure analyst and reliability engineer. He developed techniques and taught
in those areas at Fairchild Semiconductor and Hewlett-Packard. He is the founder of Accelerated
Analysis, a manufacturer and distributor of specialty failure analysis tools. David is the co-author of
Wafer Failure Analysis for Yield Enhancement . A graduate of Rensselaer Polytechnic Institute and San
Jose State University, he is a member of EDFAS and has served on various ISTFA committees. David is
a Senior Life Member of IEEE and was General Chairman of the 1983 International Reliability Physics
Symposium (IRPS).
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