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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 1 required for fast EFA on current and future process technol-
ogy nodes. Further questions and discussions were held,
includingwhat percentage of on-die cases goes to physical
versus electrical FA. This is a business decision, and it varies
based on the negotiation between the design house and
the foundry. Another questionwas asked about foreseeing
foundries being able to support the industrieswith the right
agreements in place. The response for NVidia was yes, and
that NVidia is willing to share their in-depth knowledge to
enable foundries to be successful.
Mr. Dave Budka (Intel Corp.) gave the fourth and last
presentation, “Power Debug on Fully Integrated Voltage
Regulator (FIVR) Introduced on Deep Low-Power States.”
Mr. Budkaoutlined theHaswell ULT (mobile chip) andhow it
contained an FIVR system, including the high-level reasons
why Intel did this design. With a new technology, there is
always a need to fully validate/characterize the newdesign
and how it is operating, looking for any potential issues.
Mr. Budka went on to outline how the new FIVR technol-
ogy is based on the principle of a buck converter (up to
16 phases, 90% efficient) and has a feedback mechanism
to sample workloads for different applications. It also
was the power control for seven domains dynamically, as
the chip is changing its workload and power states. Mr.
Budka discussed the need for the platform IREM system.
This system consists of an IREM optical probe tool with a
motherboard/platformsystemdocked to the table,with the
means to load and run different software applications, and
so on. Mr. Budka showed numerous IREM images for both
static and dynamic cases, demonstrating the behavior of
the FIVR domains and the data supporting the removal of
an on-package air core inductor to lower overall product
costs. Additional test cases, showing the results fromboth
electrical overstress and thermal runaway, were discussed.
Further audience discussion centered around how moth-
erboard/platform work is difficult to enable but provides
a lot of good information, especially with the capability to
run the same (or very similar) applications that original
equipment manufacturers may run.
This year’s Contactless Fault Isolation User Group had
98 attendees, representing semiconductormanufacturers,
industry suppliers, universities, and national labs. The
session had four technical presentations, each followed
by a presenter’s question-and-answer panel session. The
presentations covered a wide range of important industry
topics. Excellent presenters, panelists, and audience par-
ticipation made it another productive year for the ISTFA
Contactless Fault Isolation User Group.
The 2015 FIB User Group meeting was well attended,
with approximately 80 people representing the
failure analysis, debug, andmaterials analysis com-
munities. This year’s User Group covered three basic topic
areas: novel patterning applications, novel ion species for
transmission electron microscopy (TEM) prep and other
applications, and TEM sample preparation.
The session beganwith two presentations on novel Ga+
FIB patterning techniques. The first was by Philipp Scholz
(Berlin University of Technology, Berlin, Germany) on the
use of a Ga+ FIB to create a solid immersion lens (SIL) in the
silicon substrate to enable optical probing of subsurface
transistors. This technique increases the numerical aper-
ture for optical microscopes without having an actual SIL
lens on the scope, an application that may be necessary
if the sample substrate is too small to land a SIL lens on
the surface. This work at TU Berlin demonstrated optical
resolution down to 387 nm.
ISTFA 2015 FIB USER GROUP
Moderators: Steven Herschbein, IBM, and Richard Livengood, Intel Corporation
The secondnovel patterning presentationwas by Jason
Sanabia of Raith America, Inc. Jason presented the use
of the Raith nanoFIB Two to perform novel patterning for
various larger-area machining applications, such as nano-
fluidic devices, plasmonic devices, nanopores, x-ray zone
plates, and other novel direct-write applications. One of
the biggest challenges is nonuniform machining artifacts
that occur during mosaic patterning, where two pattern
regions must be connected. When stitching two adjacent
FIB-machined areas together, there is an overmill at the
transition point due to the abrupt milling step of the first
milled areawith the secondmilled area. A possible solution
to reduce these artifacts is the application of ion milling
in much lower doses, with or without overlapping edges.
Jason demonstrated that edge-to-edge artifacts could be
greatly reduced if thematerial removal was amortized over
severalmillingpasses. Another solution is tomove the stage
under the ionbeam, thus expanding theeffective ionmilling
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