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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 1 sample in the TEM, it was found that the suspected contact
was partiallymissing silicide. A lengthwise cross-sectional
TEMconfirmed this finding. To confirmthatmissing silicide
would cause this failure, it was simulated in the design and
was corroborated this way. Even partially missing silicide
can cause the cell to become unstable at high voltage.
A question from the audience was raised: Can the
• Output: Id, Vd reflect current transformer-loop resis-
tance. In the case of an extra diode at the source/
drain, Id-Vg analysis would miss the electrical
signature.
• For a gate stack failure, sweep direct current versus
alternating current. Pulsed IV gives a signature of static/
read noise margin.
For a 6T cell, I-V data at the contact can reveal a pull-
down NMOS mismatch. Having no window for read noise
margin proves that it is a single-bit failure. The data
analysis for singleMOS transistors and single-bit SRAMwas
included. In using nanoprobing to characterize MOSFETs,
onemust look at not only the output curves (Id-Vd) but also
the transfer characteristics (Id-Vg). For a single-bit SRAM, the
complete analysis should include the following I-V data:
transfer gate loop, output source drain, and pulsed I-V
(and/or noisemargin) atmetal 1. Also, capacitance-voltage
data enhance gate/channel analysis. Pulsed I-V helps with
speed-related issues, and pulsed noisemargin is necessary
to detect resistive gates.
StephanKleindiekofKleindiekNanotechnik,Reutlingen,
Germany, presentednew techniques for successful probing
experiments (e.g., characterizing a transistor). Success
depends on three factors:
• Clean samples, probe tips, and environment
• High-precision positioning capability
• High stability (low drift)
A probing platformwith compact dimensions provides
these features. Results on 14 nm technology were pre-
sented. Prior to transistor characterization lies the task of
locating the area of interest.
Current imaging (CI) is a method for visualizing/
mapping current levels on the sample surface. Thismethod
involves the use of a nanomanipulator to land a probe tip
on the sample surface and gently sweep the biased tip
across the surface while recording the resulting current
flow. The surface is scanned similar to a conductive AFM
but without the force feedback. While scanning, the probe
is lowered and stopped when the signal is detected.
Correlative microscopy (typically SEM) can confirm the
area. The current path can be configured in variousways by
using additional (stationary) probe tips or the samplebulk’s
contact. The resulting current maps yield insight into the
sample’s behavior. Recent advances using the CI technique
were presented. An example of a leaky gate was shown, as
was abeneficial side effect of this technique, which is clean-
ing out the surface of the sample like a windshield wiper!
“CAN THE MISSING SILICIDE ALSO BE IN
OTHER AREAS BUT NOT DETECTED?
THE ANSWER WAS YES, IT CAN.”
missing silicide also be in other areas but not detected?
The answer was yes, it can.
Shih-Hsin Chang of MA-tek, Hsinchu, Taiwan, also
spoke of the challenges facing failure analysis, especially
in how to localize failures in the nanoscale. Four cases
were introduced to demonstrate how to use an AFM-based
nanoprober (AFP) toachieve this goal. With the helpof pico-
current imaging, scanning capacitance microscopy, and
IV measurements, the location of failures can be precisely
identified and the properties of failures can be successfully
probed. Sample preparation, on the other hand, is also a
difficult task. The probing results on samples prepared by
mechanical polish as well as by plasma FIB were demon-
strated. The AFP offers high resolution and can have up
to eight probe heads and a contact resistance of less than
30 Ω. In some cases, a failing part must be compared to
a standard reference part. Contact resistance is another
issue that can be reduced by using a Kelvin probe setup.
If localization is lacking, a picocurrent image can narrow
down the area, and this can be subsequently marked with
a probe and then sectioned for TEM imaging analysis. The
probe is used to mark the area of interest.
LiLung Lai of SMIC, Shanghai, China, shared his strat-
egy of device analysis via nanoprobing methodology. In
an organization, who decides how to proceed in device
analysis? It helps to have a predefined methodology. Can
it be done automatically ormanually? Is the analysis direct
current only or also alternating current? Some fundamen-
tals were presented:
• Compare I-V relationships by nanoprobing
• Look at transfer versus output characteristics (Ion, Vt , Ioff)
• Transfer: Id, Vg , reflect continuous behavior for MOS
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