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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 1
FIB cross sectioning and ionmilling. The presentation was
concludedwith a case study involving a T0 package failure,
where the package FA flow, involving a few state-of-the-art
FA toolsets, was followed. The summary highlighted the
growing importance of 3-D x-ray for FA turnaround-time
reduction on complex packages as well as plasma FIB for
successful package preparation.
Power semiconductor sample-preparation trends in
relation to advances in semiconductor architecture and
advanced power package design and materials were dis-
cussed next. Ian Kearney of Texas Instruments presented
“General Power MOSFET/3-D Stacked Die Sample Prep.”
He gave an overviewof the popular industry FA techniques
used on discretes and integrated power devices.
Ian presented various package polishing techniques
and discussed a few FA case studies involving discrete
and integrated power chip-scale package/land grid array
and 3-D stacked-dice packaged devices. The case studies
highlighted package FA challenges involving solder voiding
and solder profiling, wire sag isolation, solder cracking,
and 3-D multichip-module package decapsulation after
temperature cycling (MIP), to name a few.
After the presentations, the session continued with a
question-and-answer panel discussion. Several involved
conversations took place among the User Group attend-
ees and the panelists about sample-prep challenges and
limitations and the opportunities for future trends and
directions. Several discussions continued after the session
was over. Many thanks to all the participants who stayed
until the very end, and special thanks to Digit Concept for
their support.
Alarge number of presenters covered a broad spec-
trumon topics surrounding nanoprobing during the
Nanoprobing User Group.
Sweta Pendyala of Globalfoundries started the presen-
tations and addressed how to reduce the time it takes for
nanoprobing to localize a defect. Localization techniques
such as scanning electronmicroscopy (SEM)-based voltage
contrast and atomic forcemicroscopy (AFM)-based current
imaging have been employed to localize defects on bulk
semiconductor technology. These techniques cannot be
used “as is” for localizing defects on silicon-on-insulator
(SOI) technology because there is no direct path to ground
from the SOI to the sample chuck. Two different atomic
force probe (AFP)-based localization techniques have
been successfully implemented to localize defects on SOI
technology. The first technique is capacitance-based top-
down scanning capacitance localization. In this technique,
a low-frequency alternating current signal on the substrate
causes a change in capacitance. The amplitude of the
signal indicates the amount of dopant and the phase type
of dopant. Using a reference part, scanning capacitance
can pinpoint the defect area, and then nanoprobing can
be performed there. The second technique is a current-
imaging-based picocurrent localization technique that
has been modified to localize defects on SOI. The AFP
provides a current map, and, in SOI, the path to ground
ISTFA 2015 NANOPROBING USER GROUP
Moderators: John Sanders, DCG Systems, and Nicholas Antoniou, ReVera, Inc.
can be provided through the part by using the defect as
a detector. For example, one can bias the ground rail and
ground V dd. In summary, scanning capacitance can be used
on SOI and is highly sensitive but can cause false positives.
Picocurrent localization needs a path to ground, but if one
can be found, it rarely gives a false positive.
Two questions were asked by the audience:
• What is the tolerance of the topography? Answer: 15
to 20 nm
• What is the typical raster time? Answer: 2 min
Vinod Narang of AMD Singapore presented the failure
analysis for advancedmicroprocessors. Soft fails, in which
an SRAM bit cell exhibits voltage sensitivity, are difficult to
analyze. In this work, SEM-based nanoprobing followed
by transmission electron microscopy (TEM) was shown
to successfully identify the root cause of the failure. The
work also highlights that collaboration is needed with
design teams to simulate the fails. This helps to explain
the nanoprobing andphysical failure analysis observations
to further confirm and validate the findings. A case study
was presented for a built-in self-test soft failure, an SRAM
double bit that failed at high voltage and high tempera-
ture. By probing each transistor in the SRAM cell, a single
transistor was found with low I dsat. A cross-sectional TEM
image of the gate did not explain this failure. By tilting the
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