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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 1
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A SUMMARY OF THE ISTFA 2015 PANEL DISCUSSION:
FIRST-SILICON DEBUG
Felix Beaudoin
Globalfoundries, Malta, NY
EDFAAO (2016) 1:S1-S8 1537-0755/$19.00 ©ASM International®
The ISTFA 2015 Panel Discussion was dedicated to
the challenge of performing failure analysis (FA)
and debug of first-silicon products. Time-to-market
of new products is critical, and product systematic failure
can result in months of delay. High pressure is on the FA
laboratory, which is expected to find root cause in days, if
not hours. The panel presentations discussedmethodolo-
gies for performing first-silicon debug and the importance
of setting up the right culture and environment for success.
The panel members were Ryan Ross of NASA Jet
Propulsion Laboratory, Pasadena, Calif.; Geir Eide of
Mentor Graphics, Wilsonville, Ore.; Izak Kapilevich of DCG,
Chandler, Ariz.; and Joe Lebowitz of Maxim. The panel was
moderated by Tracy Myers, ON
Semiconductor, Gresham, Ore.
The panel opened with a
presentation by Ryan Ross on
the complex task of planning for
new product introduction (NPI)
to enable successful first-silicon
debug. He argued that ultrafast
NPI issue identification is a high-
visibility opportunity to shine or
fail. Ryan highlighted that an FA
plan must be started 6 months prior to a new product and
should include deliverables such as layout, test conditions
and test program, automatic test pattern generator diag-
nostic package,memory logical tophysical translation, and
probe card and load board to enable dynamic FA. Planning
should start approximately 18 months in advance if new
tooling, process flow, andprocedures are required to tackle
future FA challenges on upcoming technologies.
Geir Eide then focused on the test perspective of first-
silicon debug. He stated that effective and automated
diagnosis of a test failure requires an accurate model of
the actual fail mechanism. However, design marginalities,
which are often involved in new product failures, are hard
to model. Geir presented two trends that further increase
the diagnosis challenge: the introduction of more complex
design-for-test structures, and the growing number and
complexity of on-chip instruments. On the bright side, he
presented the IEEE1687 IJTAGstandard that enables access
to any component within a system-on-chipwithout a priori
knowledge through instrument-specific instructions.
Izak Kapilevich followed with an introduction on the
FA organization and described the FA process flow used
to identify failure root cause. He argued that when a new
device is introducedwith a newproblem, the FA labwill typ-
ically try all static anddynamic optical-based techniques to
localize the failure to a smaller area of interest to improve
the physical FA success rate. He also emphasized the impor-
tance of wafer-level testing to
perform quick die-to-die analy-
sis to improve turnaround times.
Izak presented a comparison
between three companies and
correlated their respective first-
silicon debug time to root cause
to their level of FA readiness.
Joe Lebowitz concluded the
panel presentations with five
examples that illustrated the critical importance of test and
FA for first-silicon debug. In his opinion, the fab ultimately
owns the yield issue even if the root cause can be design,
test, or FA. The first case study he presented highlighted a
yield loss due to a frequency shift on amulticore processor
that was ultimately traced back to a test sequence change
to improve test time. Thedie-heatingdifferences shifted the
measured F max. The corrective action was to put in place a
change control for all changes, including test. In another
example, Joe discusseda 0 kmautomotive customer return
that failed for missing-metal defects. Root-cause analysis
identified that, due to incomplete test coverage, the fab
defects could not be screened in the specific failing block.
Containment actionwas to implement 100% in-line defect
scans of specific care area at allmetal layers. Joe concluded
“THE PANEL PRESENTATIONS
DISCUSSED METHODOLOGIES
FOR PERFORMING FIRST-SILICON
DEBUG AND THE IMPORTANCE OF
SETTING UP THE RIGHT CULTURE AND
ENVIRONMENT FOR SUCCESS. ”