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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 4

2

PURPOSE:

To provide a technical condensation of

information of interest to electronic device failure

analysis technicians, engineers, and managers.

Felix Beaudoin

Editor/Globalfoundries; felix.beaudoin@

globalfoundries.com

Scott D. Henry

Publisher

Mary Anne Fleming

Manager, Technical Journals

Kelly Sukol

Production Supervisor

Liz Marquard

Managing Editor

ASSOCIATE EDITORS

Michael R. Bruce

Consultant

David L. Burgess

Accelerated Analysis

Lihong Cao

ASE Group

Jiann Min Chin

Advanced Micro Devices Singapore

Edward I. Cole, Jr.

Sandia National Labs

James J. Demarest

IBM

Christopher L. Henderson

Semitracks Inc.

Jason M. Higgins

TSMC (Wafertech)

Bobby Hooghan

Weatherford Laboratories

Eckhard Langer

Globalfoundries

Philippe H.G. Perdu

CNES France

Rose M. Ring

Qorvo, Inc.

H.S. Silvus, Jr.

Southwest Research Institute

E. Jan Vardaman

TechSearch International, Inc.

Martin Versen

University of Applied Sciences Rosenheim, Germany

Lawrence C. Wagner

LWSN Consulting Inc.

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Electronic Device Failure Analysis

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T

he ever-increasing financial stakes faced by semi-

conductor high-volumemanufacturing (HVM) on

moving to the next node have propelled failure analysis (FA) to levels

unimaginable even 20 years ago. The primary driving forces behind this can

be summed up as resulting from:

• Increased process complexity (new materials and structures)

• Increased number of mask steps per device node

• Tighter process control

The increased process complexity derives from the fact that 20 years

ago shrinkage simply entailed shrinkage. However, excessive leakage (short

channel effects, etc.) in logic devices brought an end to this Dennard scaling

at approximately the 130 nm node (launched in 2001, at which time copper

interconnects and low-k dielectrics were already mainstream). Progressing

beyond 130 nm required the introduction of strain engineering, high-kmetal

gate stacks, and movement to 3-D structures.

The increased number of mask steps arises from the increased process

complexity discussed above, and the fact that ArF lithography (193 nmwave-

length) has been used throughout the 90 to 14 nm logic nodes, with the latter

being well beyond the dry ArF lithography diffraction limit. Surpassing this

limit has required the introduction of new approaches, such as immersion

lithography (193

i

), phase shift masks (PSM), optical proximity correction

(OPC), litho-etch-litho-etch (LELE) techniques, self-aligned double pattern-

ing (SADP), and so on. Moving to 7 nmwithout the use of extreme ultraviolet

(EUV) lithography will likely require the extension of LELE, that is, LELELELE,

implementation of self-aligned quadruple patterning (SAQP), and so on.

These processes have driven the number of mask steps from ~50 steps for

the 28 nmnode when using OPC, PSM, 193

i

, etc., to ~66 steps for 14 nmwhen

using OPC, 193

i

, PSM, SADP, etc., to an expected ~80 steps for the 7 nm node

if not using EUV.

Tighter process control drives the need for additional metrology andmore

stringent control of contamination/particles. In this vein, airborne particle

sizes have not changed over the last 20 years, which implies that their impact

should increase in a quadratic fashion with each subsequent node. In addi-

tion, smaller particles are having a greater impact.

The scope of FA labs can encompass everything fromthe chemical analysis

of incoming chemicals, qualification/matching of process tools/recipes/envi-

ronment, to the evaluation of the root cause of electrical issues noted at the

unfinished die through to the shipped package level. As withHVM, the FA labs

have had to derive newanalytical solutions to the questions raised onmoving

NOVEMBER 2016

|

VOLUME 18

|

ISSUE 4

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS

ELECTRONIC DEVICE

FAILURE ANALYSIS

(continued on page 45)

GUEST EDITORIAL

FAILURE ANALYSIS IN HIGH-VOLUME

MANUFACTURING

P.A.W. van der Heide, Globalfoundries

paul.vanderheide@globalfoundries.com