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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 2
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PURPOSE: To provide a technical condensation of
information of interest to electronic device failure
analysis technicians, engineers, and managers.
Felix Beaudoin
Editor/Globalfoundries;
Scott D. Henry
Publisher
Mary Anne Fleming
Manager, Technical Journals
Annie Beck
Production Supervisor
Liz Marquard
Managing Editor
ASSOCIATE EDITORS
Michael R. Bruce
Consultant
David L. Burgess
Accelerated Analysis
Lihong Cao
Advanced Micro Devices
Jiann Min Chin
Advanced Micro Devices Singapore
Edward I. Cole, Jr.
Sandia National Labs
James J. Demarest
IBM
Christopher L. Henderson
Semitracks Inc.
Jason M. Higgins
TSMC (Wafertech)
Bobby Hooghan
Weatherford Laboratories
Eckhard Langer
Globalfoundries
Philippe H.G. Perdu
CNES France
Rose M. Ring
Globalfoundries
H.S. Silvus, Jr.
Southwest Research Institute
E. Jan Vardaman
TechSearch International, Inc.
Martin Versen
University of Applied Sciences Rosenheim, Germany
Lawrence C. Wagner
LWSN Consulting Inc.
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Technologies are still moving to the nanometer
scale, with the technology node already at 14 nm,
new materials with high-k dielectric and metal
gates, new transistor architecture with FinFETs, complex multicore architec-
tures, and very high-density integration. All the design tools, including design
for test, design formanufacturing, and design-in reliability, have been refined
and merged to speed up time-to-market and improve yield and reliability,
while the latest wafer fabs are already well equipped to manufacture up-to-
date and future very-large-scale integration (VLSI). Nevertheless, failure and
technological analyses are still mandatory to solve unforeseen issues and
to optimize the whole process. This creates incredible challenges for tool
manufacturers to fulfill the needed optical resolution for backside analysis, to
develop new nanoprobing tools for electrical characterization, and to target
ultimate physical and chemical resolution (analytical transmission electron
microscopy, atomic probe, etc.). Developing these tools is more and more
expensive, while up-to-datewafer fab facilities and the design cost of ultimate
VLSI allow fewer and fewer players and factories into the market. One of the
results is the high cost of tools, and another result, more linked to device
technology, is the need for more and more skilled specialists to manage the
analysis and to interpret the analysis results. Fortunately, the mass-market
economic impact is so high that integrated circuit (IC) manufacturers are
continuing the effort to obtain the necessary tools and to pay the right price
for them. Therefore, there is a kind of balance that smooths the trends of
fewer customers and more expensive tools on one side versus motivated IC
manufacturers on the other. In this ultimate technology field, today’s tools
aremeeting our needs, andwe can remain quite confident for the next several
years, but not forever, regarding the technical, scientific, and cost challenges
that tool manufacturers face in developing new tools. This problemhas been
clearly identified, and the first Circuit Analysis Tool program has been set up
to help develop needed tools and techniques.[1]
However, we cannot reduce failure analysis (FA) to this market. There are
other concerns that challenge the tools and techniques we have, primarily
the more-than-Moore field, which has both 3-D integration and multiphys-
ics components. If we consider 3-D integration, one of the main challenges
faced by FA engineers is the lack of transparency in 3-D devices. So far, only
electromagnetic fields, acoustic waves, thermal waves, x-rays, and electrical
signaling through conductors canbe used. Impressive efforts have beenmade
by tool manufacturers to address shorts and opens. Magnetic microscopy,
lock-in thermography, and terahertz reflectometry have been successfully
used, but is there any tool and technique capable of localizing soft defects
MAY 2016 | VOLUME 18 | ISSUE 2
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS
ELECTRONIC DEVICE
FAILURE ANALYSIS
(continued on page 51)
GUEST EDITORIAL
ARE TODAY’S TOOLS MEETING FA’S NEEDS?
Philippe Perdu, CNES France