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complexity as all of these issues interact with one another.
To address some of these issues, electronic design au-
tomation (EDA) tool providers are already offering advice
related to design flow and other solutions to difficult tech-
nical challenges. Beyond these design flow modifications,
however, developers can also apply FIB circuit edit at the
prototype stage during debug. The same techniques can
also be employed to explore design optimization opportu-
nities, enabling developers to quickly and inexpensively
create, test, and validate physical prototypes before com-
mitting to the high cost or lengthy timetables of a full mask
spin. FIB-edited device prototypes can then be used on a
one-time basis to guide mask modifications, as an alterna-
tive to successive trial-and-error mask versions.
With today’s solutions, it is possible to edit circuits fab-
ricated with 28 nm and smaller technology nodes that fea-
ture multiple-layer metal stacks and occupy flip chip and
other advanced chip scale form factors. To perform the
edits, a nanoscale-resolution, gallium (Ga+) ion beam is
used in the process of imaging, etching, and depositing ma-
terials on the IC. This is done with an extremely high level
of precision. To cut and connect circuitry within the live
device, material is removed and deposited, and the same
process can also be employed to create probe points that
are used for electrical testing (Fig. 3). Advances in tools,
methodologies, and techniques have improved beam guid-
ance, enabling operators to perform more intricate opera-
tions in smaller areas, on both the back and front sides of
the device, and for handling copper layers.
To locate areas of interest, the FIB tool is coupled to a
CAD navigation system and the designer’s graphic data-
base system (GDS) files are typically used to navigate to
the precise area. This provides a very precise method for
finding subsurface features and ensuring that the right
edits are made (Fig. 4). One of the most important require-
ments for a successful FIB circuit edit is the ability to accu-
rately position the beam.
A variety of valuable applications for FIB circuit edit
exist at every available commercial node, including verify-
ing a design change on the tester and validating that change
at the system board level. The process can be implemented
both at the simulation stage and later during de-bug to op-
timize success rates during the IC design process (Fig. 5).
Typical applications include debugging and optimizing de-
vices in production, exploring and validating design
changes, and prototyping new devices without costly and
time-consuming mask set fabrication. FIB circuit edit also
can be used to scale fixes to a handful or more devices to
provide samples to internal test, validation, and qualifica-
tion teams and even customers. Finally, FIB circuit edit can
be used to accelerate time-to-market, speeding up the en-
tire cycle for getting customers into production and avoid-
ing loss of reputation or late penalties, or keeping potential
competitors from getting their foot in the door.
Electronic system failures are becoming increasingly
difficult and expensive to identify, diagnose, and resolve.
The stakes have never been higher to quickly find and fix
them before they create problems. This requires a compre-
hensive, multidisciplinary electronic system failure analy-
sis methodology and workflow that extends from the com-
ponent to system level and is backed by specialized
expertise and equipment. Meanwhile, the challenges asso-
ciated with IC design verification and validation continue
to intensify as nanoscale geometries move downward.
Adding FIB circuit edit to an overall failure analysis and
resolution arsenal can significantly increase design success
rates and preempt failures before they happen, by improv-
ing debug and validation, and making it easier to explore
design optimization opportunities without committing to
a full mask spin.
For more information:
Taqi Mohiuddin is senior director of
marketing, Evans Analytical Group (EAG) Inc., 810 Kifer Rd.,
Sunnyvale, CA 94086, 408.530.3500,
eag.com.
ADVANCED MATERIALS & PROCESSES •
AUGUST 2014
25
Fig. 5 —
Process flow for FIB circuit edit.
Design
validation
Production
Prototype
Test
Isolate
bug
FIB
circuit
edit
Mask
change