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ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 3
54
GUEST COLUMNIST
2.5- AND 3-D TSV TECHNOLOGY APPLICATIONS AND
FAILURE ANALYSIS CHALLENGES
Lihong Cao, Consultant
cao.lihong@yahoo.comT
he semiconductor industry has followed Moore’s
law in the last four decades. However, transistor
performance improvement will be limited, and
designers will not see doubling of frequency every two
years. The need for increased performance and further
miniaturization has driven the development of advanced
packaging solutions, such as fan-inwafer-level chip-scale
packaging, fan-out wafer-level packaging, wire-bonded
stacked dice, and package-on-package. These technolo-
gies are used in mass production and provide significant
benefits in form factor but may not give the desired
improvement in die-to-die bandwidth. Recently, 3-D inte-
grated circuits (ICs) that employ vertical through-silicon
vias (TSVs) for connecting each die have been proposed. It
is an alternative solution to existing package-on-package
and system-in-package processes.
The use of 3-D chip stacking with TSV technology
promises future improvements, such as reduced signal
delay and greater bandwidth, alongwith the possibility of
allowing heterogeneous integration of process technolo-
gies, a small form factor, and higher speeds with lower
power consumption than designs with multiple chips
on a printed circuit board. In addition, compared with
traditional 2-D multicore or many-core architectures,
the 3-D IC can address the major memory bandwidth
problem by stacked memory architecture. In June 2015,
Advanced Micro Devices launched the first 2.5-D TSV Fiji
product (RadeonFury),which incorporatesDRAMs stacked
vertically on each other (high bandwidthmemory) and 22
discrete dicemanufacturedby various companies that are
integrated into one single package. It is the first TSV with
microbumps for die stacking used in the graphics market
with implementation of high-volumemanufacturing. The
2.5-D TSV Fiji product has delivered faster performance
than the previous-generation GDDR5 technology.
Tremendouswork has beendone so that products can
bemanufactured using 3-D silicon integration technology.
Many challenges have been addressed, including design
complexity, electrical signal integrity, thermal manage-
ment, heterogeneous die integration, manufacturing
yield, reliability, and quality. To resolve issues and find
solutions, failure root-cause analysis is very critical to
ensuring successful 3-D IC silicon integration.
Current failure analysis techniques and tools are well
established to support 2-D products. However, they have
not beenwidely developed for 2.5- and 3-D TSV products,
and there are still many unresolved challenges.
One of the first challenges to be addressed is TSV
inspection. Typical TSV dimensions are 5 to 10 μm in
diameter, with aspect ratios preferably around 10 ormore.
It is not an easy task to etch and properly fill TSVs having
such large aspect ratios. Some of the new challenges are
metrology and inspection for TSVs and wafer backside
processing control, as well as multilevel dice stacking.
Currently, visual inspection with infrared interferometry
is the common methodology used in manufacturing pro-
duction; however, it cannot capture all defects, such as
TSV voids or insulator defects (pinholes) inside the TSVs.
Research revealed that high-frequency scanning acoustic
microscopy (SAM) (gigahertz range) and 3-D x-ray-based
inspection systems can be used for detecting TSV voids
approximately 1 μm or more in diameter. Another new
approach for destructiveanalysis inspectionof TSVdefects
is the plasma focused ion beam (FIB), which can produce
high throughput with approximately 50
×
faster milling
rates compared to conventional dual-beam FIB for pre-
paring a cross section. Several FIB vendors, such as FEI,
“RECENTLY, 3-D INTEGRATED CIRCUITS
(ICs) THAT EMPLOY VERTICAL THROUGH-
SILICON VIAS (TSVs) FOR CONNECTING
EACH DIE HAVE BEEN PROPOSED. IT IS
AN ALTERNATIVE SOLUTION TO EXISTING
PACKAGE-ON-PACKAGE AND SYSTEM-IN-
PACKAGE PROCESSES.”