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edfas.org
ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 18 NO. 2
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CANDIDATE PROFILES
CONTINUED FROM
PAGE 32
VISION STATEMENT
“EDFAS needs to bemore involved in the further devel-
opment of industrial procedures related to failure analysis,
for example, 8D reports. My personal goal is to push EDFAS
to develop toward “EDSFAS—Electron Device and System
Failure Analysis Society.” The failure analysis community
of the future needs to extend its scope to a system-level
view. The more complex the supply chains become, the
more root cause becomes involved and must be consid-
ered. Besides the classic device failure analysis, whichwill
always be limited by the actual available state-of-the-art
analysis technologies, failure anamnesis and application
characterization shall become more andmore important
to achieve the goal of root-cause discovery and making
electronics more reliable.”
Ted Lundquist,
consul-
tant, previously served as Chief
Technology Officer, Director of
Technology, and Applications
Manager at DCG Systems Inc.
in Fremont, Calif. (2008-2015).
Prior to that, hewas Applications
Manager at Credence Systems
Corp., Sunnyvale, Calif., and also at NPTest, Inc. of San
Jose. Tedworked at Schlumberger ATE from1994 to 2003
as an Applications Manager and Engineer. He received a
Ph.D. in physics from the University of Maryland and has
three FA patents.
Ted has been amember of EDFAS since 1997 andwas a
guest speaker at the first EDFAS-Taiwan Chapter meeting.
He has been a reviewer of FA-related journals, led teams to
win IARPA Circuit Analysis Tools contract awards, and has
been a guest speaker at TSMC’s Failure AnalysisWorkshop
(2014) and the LSI Testing Symposium in Osaka, Japan
(2010). He served as Circuit Edit Session Chair at ISTFA
2008-2011, was apanel expert for ISTFA2011’s “Finding the
Invisible Defect,” and is a profile author of ISTFA papers.
VISION STATEMENT
“The goal of EDFASneeds tobe inmaximizing the value
delivered to our members. EDFAS recently established
affiliations with other Societies interested in the failure
analysis of electronic devices, such as IEEE-IPFA, IEEE-
ESREF, and EUFANET. Could ISTFA sponsor FA sessions at
other conferences, suchas IEEE-IRPS, IEEE-ITC, IEEE-DATE,
and so on, or work together with them?We could be deliv-
ering value to our members at other venues.
A challenge for many members is overcoming objec-
tions by their management when requesting to attend
ISTFA. The Board of Directors needs to make it easier for
upper management to approve attendance. Recently,
failure analysis tools have been migrating to the fab lab,
where they are being used for yield learning. A yield learn-
ing sessionmight attract financial analysts and then catch
the attention of upper management. Many companies
have held small seminars on advanced topics in various
IC-centric locations. These are typically well attended
and are quite dynamic because they are small. Perhaps
seminars can be sponsored and organized locally by
EDFAS chapters but supported by the Society, with talent
recruited by EDFAS.”
Ryan Ross
manages the
Analysis and Test Laboratory at
NASA’s Jet Propulsion Laboratory
(JPL), Pasadena, Calif., where he
leads a team providing techni-
cal services to the JPL campus,
enabling root-cause failure analy-
sis, destructive physical analysis,
extreme-temperature environ-
mental testing emulating Martian conditions, electronic
parts screening, and standard analytical services.
Prior to joining JPL in 2015, Ryan was one of the
initial employees at Globalfoundries’ greenfield startup
Fab 8 foundry in New York, where he created a state-
of-the-art Product Failure Analysis team. Ryan served
as Globalfoundries’ corporate representative on the
SEMATECH Integrated Circuit Failure Analysis Council
as member-at-large, Vice-Chair (2013), and Chair (2014),
and served on the SEMATECH Package and Interconnect
Failure Analysis Council.
Ryan worked for more than 10 years at Motorola
Semiconductor, which later became Freescale Semicon
ductor (and now is part of NXP). In 2003, he accepted an
assignment at the Crolles2 Alliance in France. In 2006,
he joined the Tempe Technology Design Debug Lab and
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