edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 40 Transactions on Instrumentation and Measurement, 2025, 74, p. 1, doi.org/10.1109/TIM.2025.3602567. • J. Souto, et al: “About the Influence of Temperature Operation and Packaging Stress on the Threshold for Catastrophic Optical Damage in Laser Diodes,” Microelectronics Reliability, 2025, 168, p. 115695, doi.org/10.1016/j.microrel.2025.115695. • K.S. Woo, et al.: “[Review:] Role of Heat in PostSilicon Electronics,” Appl. Phys. Rev., 2025, 12, p. 031323, doi.org/10.1063/5.0258988. • S. Yang, et al.: “An Informer Network-Based Circuit Boards Fault Detection Method using Infrared Temperature Series,” Microelectronics Reliability, 2025, 175, p. 115890, doi.org/10.1016/j.microrel. 2025.115890. • J. Yuan, et al.: “[Review:] An Overview of Infrared Thermography for Inspection of Solder Joint in Electronic Devices,” Infrared Physics & Technology, 2026, 155, p. 106508, doi.org/10.1016/j.infrared. 2026.106508. • C. Zhao, et al.: “ThermoVision: Nondestructive Defect Mapping in 3D Stacked Dies via Surface Thermography and Deep Learning,” IEEE Transactions on Components, Packaging and Manufacturing Technology, 2026, 16, p. 757, doi.org/10.1109/TCPMT.2026.3661910. • J. Zhou, et al.: “Recent Advances in Device-Level Thermal Management Technologies for Wide Bandgap Semiconductor: A Review,” IEEE Transactions on Electron Devices, 2025, 72, p. 2769, doi.org/10.1109/TED.2025.3562506. • G. Zhu, et al.: “A Comparative Review of Junction Temperature Monitoring for SiC-Based Power Semiconductor Devices,” IEEE Transactions on Device and Materials Reliability, 2026, 26, p. 409, doi.org/10.1109/TDMR.2026.3689949. • P. Zhu, et al.: “Defect Detectability Based on Square Wave Lock-In Thermography,” Appl. Opt., 2022, 61, p. 6134, doi.org/10.1364/AO.460385. ABOUT THE COVER All images are from the 2025 EDFAS Photo Contest. Images and captions have been edited from original submitted entries. Top left: Autum Bloom: Mold compound filler particle damage to passivation from compressive stresses. The damage has a characteristic divot in the center and passivation cracks emanating from it. Acid has selectively entered through the cracks and delineated the interface between underside of passivation and top of metal giving it a flower like appearance. Photo by Raj Kabadi, Microchip Technology Inc., Second Place Winner, Color Images. Top middle: The Bonsai Effect: Tiny Tree, Massive Stress. Electrical overstress damage on ESD block/circuit. Photo by John Dave Asilo, Analog Devices Inc., Second Place Winner, Black and White Images. Top right: The title “The girl in the MIM-rror” portrays the side profile of a girl as seen through a mirror. The “MIM-rror” pertains to a metal-insulator-metal (MIM) capacitor that serves as the mirror in the image. Photo by Realyn Macatangay, Analog Devices Inc., Third Place Winner, Color Images. Middle left: SEM Safari: Spotting the Elusive Poly-perched Hummingbird. An SEM image reveals a fabrication defect resembling a hummingbird perched on a polysilicon structure. Though a defect was discovered, the hummingbird’s quest for nectar came up dry. Photo by Kyle Julius Lozano, Analog Devices Inc., Third Place Winner, Black and White Images. Middle right: Swoosh in Chip: Stress amplification at trench corners induced dislocations shown in this STEM-BF image. The right-side dislocation had punched through the reverse biased pn-junction near the NMOSFET drain contact, causing source-to-drain leakage. Strikingly, the left dislocation arcs in a shape that is reminiscent of a familiar swoosh seen far beyond the lab. Photo by Wentao Qin, Microchip Technology Inc., Second Place Winner, False Color Images. Bottom: Architectures in Copper: 3D render of hybrid copper bonding between a CPU core and its VCache acquired using x-ray nano-CT. The interconnects have a diameter of 1.5 µm, a length of 15 µm, and layers at the top and bottom contain micron and sub-micron sized structures. Photo by Till Dreier, Excillum, Third Place Winner, False Color Images.
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