edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 3 40 GUEST EDITORIAL CONTINUED FROM PAGE 2 EUV PTYCHOGRAPHIC REFLECTOMETRY: IMPURITIES AND DISORDER AT BURIED INTERFACES There is an unmet need for nondestructive, noncontact techniques capable of characterizing buried interface structure, including dopant profiles, impurity distributions, interface diffusion, and roughness, in nanostructured semiconductor materials and devices. This project develops a new instrument that provides element-specific structural information nondestructively, with a field of view up to three orders of magnitude larger than those of TEM and atom probe tomography (APT). This aims to enable rapid, statistically valid analysis of meaningful “real-world” samples with a depth resolution of approximately 1 nm and lateral spatial resolution approaching 20 nm. ATOM PROBE TOMOGRAPHY: NANOSTRUCTURED SEMICONDUCTOR MATERIALS, INTERFACES, AND DEVICES The semiconductor industry requires sub-nanometer, quantitative elemental mapping of materials, nanoscale structures, and devices in 3D, with high analytical sensitivity, for process development, FA, and competitive engineering. While APT is recognized by the industry as arguably the most powerful method for addressing these goals and is routinely employed in the semiconductor ecosystem, there is tremendous room for improvement. This project advances APT instrumentation, experimental methodologies, data analysis, and modeling and simulation by integrating multiple wavelengths into a new instrument optimized for the materials problems facing the semiconductor industry, both now and in the future. TIME-RESOLVED EMISSION MICROSCOPY FOR CIRCUIT EVALUATION AND FAILURE ANALYSIS Circuit analysis of advanced technology nodes demands improved measurement methods capable of resolving faint signals with high spatial resolution for meaningful fault isolation.[2] Time-resolved-emission microscopy (TREM) uses photonic signals generated by transistors during switching to locate faults, but current approaches fall short in spectral sensitivity, signal-tonoise ratio, throughput, and resolution. Current work in the CHIPS Metrology portfolio is integrating innovative single-photon detectors and higher-speed, multiplexed sensors into TREM to resolve signals from many tightly packed transistors. Through the CHIPS Metrology Program, U.S. industry and government R&D partners will gain a competitive advantage relative to the rest of the world through NIST’s unique capabilities and world-class expertise. The program focuses on building partnerships, expanding education and outreach, and advancing technical solutions toward industry readiness. We encourage you to visit the program’s website to learn more about the ongoing CHIPS Metrology-funded research at NIST.[3] REFERENCES 1. As authorized in Title 15 USC 4654 Sec. 9906(e). 2. EDFAS (Electronic Device Failure Analysis Society), Microelectronics Failure Analysis Desk Reference, 7th Edition (or the latest 2024/2025 updates), ASM International. 3. CHIPS Metrology R&D projects: nist.gov/chips/research-development- programs/metrology-program. Advertise in Electronic Device Failure Analysis magazine! For information about advertising in Electronic Device Failure Analysis: KJ Johanns, Business Development Manager 440.671.3851, kj.johanns@asminternational.org Current rate card may be viewed online at asminternational.org/advertise.
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