edfas.org 29 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 TOOL INNOVATIONS (HETEROGENEOUS PACKAGING) Heterogeneous integration (HI), especially with the addition of silicon photonics, remains a complex challenge for failure analysis. The difficulties span system-level DFT/ DFD coverage, fault isolation across multiple levels— including co-packaged optics (CPO)—and maintaining die functionality, all compounded by ongoing technology scaling at the die level. The approach to fault isolation and analysis depends greatly on the specific scenario, whether the issue lies in the top die, a buried die in a 3D stack, or within interconnects between dies. On the package-level software side, productivity hinges on having a unified CAD database across all tools, including sample prep, that enables seamless navigation across all IP. Hardware tools and sample prep methods must be re-engineered to handle increasingly large package sizes (approaching 100 by 100 mm) and higher power dissipation (several kW). Current electron beam probing systems, for example, house the device in a SEM vacuum chamber, greatly restricting setup size and power dissipation. Additionally, signal probing requires incision through layers that may affect functionality, possibly in the package substrate and interposer. Therefore, new techniques for larger volume excavations and grosser (than FIB) net reconstruction are required. Addressing HI fault isolation challenges—especially for buried dies—may benefit from advances in broad ion beam milling for large-area delayering and laser-assisted selective metal deposition. Emerging techniques like circuit-level nanoprobing, which maintains functionality in larger circuit blocks for fault isolation, could also play a significant role in future failure analysis. WORKFLOWS Failure analysis workflows are becoming more complex as these disruptive technologies advance, demanding new tool innovations. Solid immersion lenses (SILs), previously focused on maximizing resolution and emissions collection, now require redesigns to accommodate closely packed chiplets on advanced packages. Future SILs must balance resolution, PEM coherence, mechanical clearance, and sample thickness tolerance, while integrating with cooling solutions. This requires a re-look at the various SIL technologies such as superhemispherical and aplanatic SILs. Conventional sample preparation workflows such as CNC milling, and mechanical grinding need to be augmented by focused ion beams, ion millers and plasma etchers (RIE/MIP) to enable functional fault isolation and nanoprobing for specific chiplets. Developing workflows that combine these techniques will be crucial for addressing the challenges in sample preparation for advanced packaging. Repackaging, including partial repackaging IRFA Council Structure for 2026-2027.
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