edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 28 INTERNATIONAL ROADMAP FOR FAILURE ANALYSIS: DIE-LEVEL ROADMAP COUNCIL Kristofor Dickson and Venkat-Krishnan Ravikumar Co-chairs, Die-Level Roadmap Council kristofor.dickson@amd.com EDFAAO (2026) 2:28-31 1537-0755/$19.00 ©ASM International® INTRODUCTION Rapid innovation in electronics, led by gateall-around (GAA) transistors, backside power delivery (BPD), 3D packaging, and AI-driven design, has transformed fault isolation—a trend set to continue with photonic circuits and quantum computing. As device architectures increase in complexity and signal pathways become more difficult to access, traditional electrical fault isolation (EFI) techniques have been expanded over time to meet higher standards for resolution, accessibility, and diagnostic fidelity. However, these methods face physical limitations, prompting consideration of broader strategies to address future challenges. The Die-Level Roadmap Council (DLRC) has thus expanded its strategic focus to address these new complexities. The DLRC, a subset of the ASM International EDFAS International Roadmap for Failure Analysis (IRFA), is collaborating with representatives from industry, academia, and tool vendors to develop integrated solutions encompassing design, test, and failure analysis beginning at early development stages. To guide this effort, the DLRC has identified six critical domains for innovation in EFI over the next five years: 1. Tool Innovations (Technology Scaling) 2. Tool Innovations (Heterogeneous Packaging) 3. Workflows 4. Test, Diagnostics, and Shift Left into Design 5. AI and Software Tools 6. Emerging Areas TOOL INNOVATIONS (TECHNOLOGY SCALING) With the rise of GAA technologies and broader adoption of BPD, laser-based probing techniques face growing limitations. Even when optical access to transistors is possible, issues like poor CAD alignment, crosstalk, and low signal-to-noise ratios increasingly reduce diagnostic accuracy. Proposed solutions include adding CAD alignment library cells to support design-for-debug (DFD) initiatives. Other approaches, such as visible light probing, originally launched a decade ago, help attenuate crosstalk but introduce challenges like latch-up and waveform distortion. These issues could potentially be mitigated by upgrading to pulse-on-demand laser systems, although such equipment remains scarce. Exploratory efforts are also underway in developing laser pump-probe techniques that could enable new ways of performing FA. Bandwidth-tunable superconducting nanowire single-photon detectors are advancing toward commercial viability, offering high-efficiency, time-resolved photon emission methods to improve localization. Complementary techniques such as thermal stimulation and thermo-reflectance imaging are also being explored, with machine learning enhancing depth estimation and spatial resolution. Meanwhile, despite test and cooling challenges due to vacuum operation, electron beam probing has returned to aid isolation of circuits in backside power technology. In addition, active nanoprobing at the library cell level is gaining traction for its ability to perform single-shot “at speed measurements” without the challenges associated with e-beam sample prep. Together, these developments reflect a broader shift toward more precise, fault isolation strategies tailored to the increasing complexity of modern semiconductor architectures.
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