edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 30 and transferring chiplets to monolithic substrates, is increasingly seen as essential for efficient yield learning and streamlined failure analysis. As the industry transitions to complementary fieldeffect transistor nodes and adopts backside power networks, optical fault isolation will face new constraints for failure analysis teams. Fault isolation will become less localized, increasing the need for nanoprobing-based approaches to characterize standard cells and partially functional circuits. Iterative nanoprobing workflows and universal sample holders that facilitate easy transfer between sample prep and nanoprobers will be critical. Current methods for high pin count and high-performance processors rely on direct docking and liquid cooling for functional analysis. However, BPD process nodes will challenge this paradigm, requiring new approaches that are compatible with vacuum chamber setups (e-beam probing) and x-ray sources (x-ray assisted device alteration). This shift will necessitate both significant redesigns of direct docking setups and the adoption of high-performance cable connections with modular test boards. These innovations will be needed to enable future workflows and maintain effective fault isolation as device architectures continue to evolve. INTEGRATING TEST AND DIAGNOSTICS INTO EARLY DESIGN As digital circuits become denser and more complex, test time reduction remains a priority. This led to the introduction of embedded deterministic test (EDT) compression and has now evolved into flexible interfaces such as streaming scan networks (SSN). SSN leverages a packetized data transmission method to optimize test bandwidth and reduce test time, but this approach severely limits internal signal observability and control as it hinders the top-level visibility of important scan signals, such as the scan clock, shift enable, and EDT update, which determine the device’s state. Additionally, the SSN hardware configuration prevents on-the-fly test vector modification and looping of test patterns needed to stimulate the device during optical fault isolation. Fault isolation on SSN requires close collaboration and development of synchronization signals from the cores that are being tested. Additionally, new design features for fault isolation such as “LVX mode” to enable laser voltage imaging and laser voltage probing are being introduced by electronic design automation vendors that make signal collection easier on scan chains. Ultimately, as package, design, and process complexity continue to rise, the traditional focus on merely detecting failures (design-for-test) is no longer sufficient. The industry now requires a more robust methodology—one that integrates the ability to locate and localize failures (design-for-diagnosis) and gain access to internal nodes (design-for-debug)—culminating in an industry-wide call for a comprehensive design for test, diagnosis, and debug approach. Furthermore, while analog diagnostics and simulations are emerging areas of research and development, their current applications are limited. AI AND SOFTWARE TOOLS As in so many fields, machine learning has emerged as a transformative tool in failure analysis. It evolved from its initial role in image recognition to a strategic enabler of diagnostic precision, virtual failure analysis, and operational efficiency. This shift has led to the adoption of a diverse array of advanced architectures tailored to address the increasing complexity of semiconductor packaging and subtle defect mechanisms. Techniques like independent component analysis, Log2Vec and Key2Vec embeddings with convolutional neural network (CNN) encoders, and signal analysis and parametric imaging have further expanded the capabilities of nondestructive imaging and runtime failure prediction. Insights from ISTFA and EDFA literature underscore the integration of these models into workflows involving 3D x-ray image reconstruction, laser voltage characterization, and CAD alignment in thermal imaging demonstrating how deep learning is reshaping failure analysis from fault isolation to physical decision-making with unprecedented speed and precision. Ultra-scalable hierarchical deep networks (uSHD) have also been proposed as a systematic and quantitative approach to spectra and image data in the field of microstructures analysis. Besides eliminating the large computational cost associated with deep CNNs, uSHD enables deeper insights from signal data, enhancing both diagnostic clarity and efficiency. In addition, large language model-based AI agents that assist domain experts in utilizing knowledge databases and identifying potential failure modes are under development. Finally, graph neural networks have demonstrated high accuracy in circuit recovery from netlists, with applications extending from failure analysis to hardware Trojan detection and localization. These are only a few examples illustrating the wide range of AI application and active research from the community on the topic. However, the deployment of machine learning in failure analysis is not without challenges. Data heterogeneity, imbalance, and scarcity—especially for rare failure
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