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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 12 3. U. Botero, et al.: “Hardware Trust and Assurance through Reverse Engineering: ASurvey andOutlook fromImage Analysis andMachine Learning Perspectives,” https://arxiv.org/abs/2002.04210v2 , 2020. 4. A. Kimura, A. Waite, J. Scholl, G. Via: “Applied Failure Analysis Tools and Techniques Towards Integrated Circuit Trust and Assurance,” ASM International, Electronic Device Failure Analysis, 23 (1), 2020. 5. A. Kimura, et al.: “From Silicon to Simulation: A Full Decomposition of a Fabricated 130 nmSerial Peripheral Interface for Establishing an Assurance Baseline Root-of-Trust,” Physical Assurance and Inspection of Electronics (PAINE), December 2020. 6. T. Doi, I.D. Marinescu, and S. Kurowaka: Advances in CMP Polishing Technologies, 1st edition, WilliamAndrewPublishing, 2012, p.15-111. 7. J. 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Hawkins: “Electronic Color Charts for Dielectric Films on Silicon,” Optics Express, 2004, 12, p. 1464-1469. 14. S. Narasimha, et. al: “High Performance 45-nmSOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” Electronic Devices Meeting, 2006, IEEE, January 2007, p.1-2. 15. P.F. Schmidt andC.W. Pearce: “ANeutron Activation Analysis Study of the Sources of Transition Group Metal Contamination in the Silicon Device Manufacturing Process,” Journal of The Electrochemical Society, 1981, 128, p. 630-636. 16. D. Tweddle, et al.: “Identificationof Colloidal Silica Polishing Induced Contamination in Silicon,” Materials Characterization, 2019, 152, p. 239-244. 17. N. Watanabe, et al.: “Investigation of Metal Contamination Induced by aTthrough Silicon via Reveal pPocess using Direct Si/Cu Grinding and Residual Metal Removal,” Japanese Journal of Applied Physics, 2016, 55, p. 06GP06. 18. K. Heo, B.J. Ree, K. Choi andM. Ree: “Structural Reliability Evaluation of Low-k Nanoporous Dielectric Interlayers Integrated into Micro- electronic Devices,” RSC Adv., 2015, 5, p. 87084-87089. 19. X. Luan, et al.: “Investigation of the Barrier Slurry with Better Defect Performance and Facilitating Post-CMP Cleaning,” Microelectronic Engineering, 2017, 170, p. 21-28. 20. Q. Xu, L. Chen, F. Yang and H. Cao: “Influence of Slurry Components on Copper CMP Performance in Alkaline Slurry,” Microelectronic Engineering, 2017, 183-184, p.1-11. 21. J. Gambino: Handbook of Thin Film Deposition, 3rd edition, Krishna Seshan, Elsevier Inc., 2012, p. 225-226. 22. 2J. Obona, et al.: “Xe Plasma FIB Delayering of IC Based on 14nm Node Technology,” Microscopy and Microanalysis, 2016, p. 56-57. A SAMPLE PREPARATION WORKFLOW FOR DELAYERING A 45 nm NODE SPI MODULE (continued from page 10) ABOUT THE AUTHORS YashPatel is a computer engineer at BattelleMemorial Institute. His research experience includes sample preparation of integrated circuits for hardware design verification and validation. He gradu- ated fromTheOhio StateUniversitywith a bachelor of science inmaterials science and engineering in 2019 and is currently pursuing a graduate degree inmaterials science through Arizona StateUniversity with a focus on nanoelectronics. Joshua Baur is a computer engineer at Battelle Memorial Institute with 14 years of experience supporting national security research. His background ranges fromhigh containment chemical and biological weapons research to his current focus in integrated circuit security research and microscopy. His current research interests are integrated circuit hardware security, and advanced electron microscopy imaging techniques. Adam Kimura is a senior cyber scientist at Battelle Memorial Institute and has beenworking in the field of trusted and assuredmicroelectronics since 2013. His research experience spans the verification and validation of integrated circuits, integrated circuit decomposition, and developing novel techniques for quantifying hardware assurance in advanced node devices. Kimura currently holds his B.S., M.S., and Ph.D. in electrical and computer engineering from The Ohio State University. Jonathan Scholl is a lead materials engineer at Battelle Memorial Institute where he works on sample preparation of integrated circuits. He has a B.S. from The Ohio State University inmaterials science and engineering specializing in electronicmaterials and aM.S. fromTheOhio StateUniversity in biomedical engineering specializing inmicro/nano devices. His research interests are in delayering advanced integrated circuits for design validation and automating sample preparation tools.