edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 4 EDFAAO (2019) 1:4-9 1537-0755/$19.00 ©ASM International ® MACHINE LEARNING INSIDE THE CELL TO SOLVE COMPLEX FINFET DEFECT MECHANISMS WITH VOLUME SCAN DIAGNOSIS Manish Sharma, Mentor, A Siemens Business, Wilsonville, Ore. Yan Pan,*GlobalFoundries, Malta, N.Y. manish_sharma@mentor.com *Now with AMD. D evice complexity is reaching an all-time high with the adoption of high aspect ratio FinFETs created using multi-patterning process technologies. Simultaneously, new product segments such as artificial intelligence (AI) and automotive are targeting advanced processes. In this dynamic environment, newand complex defectmodes are threatening the ability ofmanufacturers to rampup and sustain semiconductor quality and yield. A growing source of quality and yield problems stems from the effect of process variability on standard cells, which introduces new transistor-level defectmodes. Meanwhile, the cost of traditional failure analysis (FA) continues to skyrocket. This article details a new breakthrough in the field of scan diagnosis andmachine learning. For the first time, cell-internal defects not only can be detected and diagnosed, but also refined, clarified, and resolvedwith a root cause deconvolution (RCD) algorithm. Experimental FA results show that RCD is very effective at increasing the resolution of the diagnosis by reducing the number of suspects in cell-internal defect data. FETS, SILICON TEST AND FA As the semiconductor industry marches forward with advanced technology nodes from 14 to 10 nm, and now 7 nm and beyond, the density increase is no longer coming fromsimple planar pitch scaling. Rather, achieving higher transistor density requiresmore complex layout structures and fabrication processes. For example, now the more complex FinFET transistors with high aspect ratios are needed tomaintain performance and efficiency. For print- ing smaller thanwavelength features, multi-patterning is required for lower metal layers. Tomake library cells even smaller, contact-over-active-metal and singledummy gate techniques are used. In the future, complexity is predicted to continue increasing with the use of technologies such as gate-all-around transistors, complementary FET, and others. This implies that more defects and systematic yield issues are expected in the front-end layers that are inside library cells. We can expect an increase in the number of defects only caught at the end-of-line during final test of manufactured die. This will occur despite all the pre-silicon process simulation-based analysis, test chips, and inline yield improvement through inspection and metrology. Performing FA on defective die is the most reliable path to finding the root cause of manufacturing yield loss. However, the cost of conducting FA for defects inside cells continues to increase for several reasons. First, nondestructive optical fault isolation techniques such as laser-voltage-probing and dynamic laser stimulation are facing fundamental resolution limits due to silicon’s increasing absorption of shorter wavelength radiation. This necessitatesmore expensive physical measurements like nanoprobing. Second, when a defect is located, more expensive transmission electron microscopy (TEM) and thin (<20 nm) sample preparation are often the only viable techniques to identify and analyze the defect. Each TEM toolset costs millions of dollars and requires hours to prepare and process one sample. The industry made a significant FA equipment investment for the 22 and 16 nm generations of FinFETs, as seen in the financial reports of major equipment suppliers, e.g., FEI Company’s SEC 10K reports, 2009-2013. The escalating FA cost makes it even more imperative that each FA be successful and effective in leading to yield improvement. This, in turn, implies that there is an increased need for careful selection of failing die that aremost likely to represent main yield loss mechanisms. Without a careful die selection, the overall cost and cycle time of identifying the underlying problems causing yield loss will continue to increase.