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edfas.org 37 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 modern ICdevices, andSEM imaging is reliedon toprovide the spatial resolution required to resolve features at the finest scale. Despite the shortcomings of synchrotron- based x-ray 3-D imaging in terms of spatial resolution and accessible volume, this method has played an important role in the evolution of x-ray-based techniques to “non- destructively” analyze ICs and to extract interconnect and trace data as well as material composition informa- tion. [7] The Intelligence Advanced Research Projects Activity (IARPA) has issued a challenge through its Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program to extend the capabilities of nondestructive and destructive techniques to enable the complete depro- cessing of a modern IC device across an entire 1cm 2 die within a span of 25 days at a target resolution of 10 nm using a lab-based tool. [8] BAE Systems and its partners have taken on this challenge and are developing a tool that combines high-resolution x-ray CT tomography (X-Mode) using transition-edge sensors with ultrahigh- resolution SEM (E-Mode) on backside-thinned devices. [9] Such a hybrid approach—using electron microscopy to obtain high-resolution imaging data from the backside, where the density is highest and the structures are of the finest scale, combined with novel x-ray tomography in one laboratory-based tool—may become a key com- ponent to a deprocessing tool suite in the near future. It is conceivable that gas-assisted delayering technologies in combination with other charged particle beams could be woven into such a system to permit in situ delayering. Regardless, x-ray CT imaging technologywill remain a key component to nondestructive characterization, FA, and reverse engineering. The image panel in Fig. 1 illustrates three individual X - Z image frames representing part of the complete image series used to reconstruct the device volume. Thedatawere acquiredonaBruker Skyscan2211. AUTOMATED BACKSIDE THINNING Automated backside thinning represents a critical advance to enable the most versatile deprocessing work flow. The technology required to achieve automated backside thinning to within 1 to 3 µm of the active silicon is no small feat. It should be appreciated that a silicon die is never perfectly flat, and regardless whether it remains in the package or is extracted, it is subject to complex strain and deformation induced by thermal expansion andmechanical constraints. Moreover, during the thinning process there is relaxation and sag; therefore, it is neces- sary to continuously monitor both shape and thickness. This dynamic process requires precision laser monitor- ing coupled to feedback driving an adaptive five-axis computer numerical control (CNC) multitool. The tooling combines both grinding and polishingwith a floating tool head that follows the contoured surface of the die during the process, as schematically represented in Fig. 2. Through this automated process, an initial wafer thickness of 775 µm was thinned using the VarioMill by Varioscale, which combined automated grinding and polishing processes to achieve a final residual thickness between 1 and 2 µm across the entire die. In the case of the AMD Opteron processor, the die size is 18 × 16 mm. The residual backside silicon is sufficiently thin that it is possible to image into the active silicon and reveal the Fig. 1 Three image panels from the complete dataset series from the x-ray tomogram of an AMD Opteron chip. The x-ray CT data form the volumetric boundary of the device and provide connectivity at the level of the PCB. Fig. 2 Schematic representation of adaptive CNC five-axis machining tool head to followthe evolving shape and thickness during mechanical backside thinning