edfas.org 21 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 3D IMAGING OF INTEGRATED CIRCUITS VIA LIMITED ANGLE X-RAY TOMOGRAPHY Nathan Nakamura1, Jordan Fonseca1, Joseph W. Fowler1, Felix H. Kim1, Zachary H. Levine1, John Henry Scott1, Paul Szypryt2, Andras E. Vladar1, and Daniel S. Swetz1 1National Institute of Standards and Technology 2University of Colorado, Boulder nathan.nakamura@nist.gov EDFAAO (2026) 4:21-29 1537-0755/$19.00 ©ASM International® INTRODUCTION Modern semiconductor devices are incredibly complex, containing many material types and feature sizes spread across hundreds of layers and square millimeters of area. Physical defects introduced during fabrication, assembly, or operation in a single component or layer can compromise the functionality of the entire device. This makes defect identification and quantification critical to semiconductor fabrication but also challenging. Defect sizes can range from the nanoscale to micrometers and must be located despite this structural complexity. Postidentification, the root cause from many possible fabrication and assembly processes must be determined. Many metrology tools exist for semiconductor failure analysis, particularly within isolated device layers, but the rise of 3D structures and integration poses unique measurement challenges.[1-2] X-ray computed tomography (CT) is a measurement technique well-suited for the characterization of 3D structures. Due to the penetrative nature of x-rays, x-ray CT can image sub-surface layers without physically cutting into the device, making it a powerful approach for nondestructive FA or hardware security verification. In an x-ray CT measurement, photons are transmitted through the device under study. The intensity of the x-rays after transmission is dependent on the energy of the photons and the size, shape, and material composition of the features present.[3] This transmission data is acquired at many different projection angles, often by rotating the sample being imaged, and a 3D image of the device interior can be reconstructed.[4] CT has been used for many FA applications in the semiconductor industry, including identifying delamination and voids in bump bonds and hybrid bonding.[5-7] Despite this success, additional development work is required to bring x-ray CT to its full potential for FA. Spatial resolution, or the size of device features that can be reliably imaged, needs to reach the tens of nanometers or below to identify defects in devices with ever-decreasing feature, and thus relevant defect, sizes. Measurement speed must also improve to accelerate feedback of CT results into fabrication and assembly processes. Here, we discuss a novel approach to x-ray CT that achieves nanoscale spatial resolution and rapid imaging using a small number of projection angles relative to con- ventional CT approaches. The overall instrument design and concept is discussed, along with experimental considerations impacting the imaging resolution. Results from 3D imaging of a 130 nm node integrated circuit (IC) are shown, along with a discussion regarding the achieved image resolution. Opportunities for improvements to speed, resolution, and additional imaging capabilities are discussed. INSTRUMENT OVERVIEW The x-ray CT instrument utilizes the focused electron beam of a scanning electron microscope (SEM), a thin film metal target deposited onto the IC of interest, and a 4-megapixel hybrid photon counting detector (HPCD). The electron beam is focused onto the metal target, which generates a polychromatic x-ray focal spot. The photons pass through the IC layers and are attenuated based on their energy and the features present in the IC. The HPCD has an active area of 25,000 square millimeters and enables rapid, high-efficiency detection of the transmitted photons.[8] Prior measurements with this system utilized a superconducting x-ray spectrometer, which provides vastly improved x-ray resolving capabilities at the cost of total collection efficiency.[9] Here, the HPCD is chosen to maximize imaging speed. A schematic of this setup is
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