edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 3 38 On April 21, 2026, the Electronic Device Failure Analysis Society (EDFAS) hosted a grand Failure Analysis Workshop in Hsinchu, Taiwan. Integrated Service Technology (iST) served as a co-organizer of the event, and Danny Yu, iST chairman, opened the ceremony, warmly welcoming local and international industry leaders to the region. Yu noted that the decision by EDFAS to hold its firstever Asian technical workshop in Taiwan signifies Asia’s pivotal strategic position in the global semiconductor landscape. Through this platform, iST will collaborate with global experts to overcome the extreme packaging verification bottlenecks of the artificial intelligence (AI) era and define new failure analysis standards for AI. The forum saw a full house, attracting packaging and testing experts, chip designers, and R&D executives from across the globe. The event gathered industry leaders such as Nvidia, TSMC, and Qualcomm to discuss challenges and opportunities for complex packaging structures of the “Post-Generative AI Era.” As AI computing demands enter a period of explosive growth, fault localization within chip structures has become the ultimate hurdle in determining mass production yields and product time-to-market. During the forum, Nvidia unveiled its future vision for chip-level failure analysis workflows. With the surge in AI training and inference demands, data centers now require unprecedented high-speed transmission capabilities. Nvidia emphasized that in high-performance and highpower environments, even microscopic signal interference or packaging defects can trigger catastrophic failures. Consequently, collaboration across design, manufacturing, system-level, and product teams from the initial design phase is essential to ensure that customers receive products with zero defects. TAIWAN HOSTS EDFAS WORKSHOP INTERNATIONAL EDFAS FA WORKSHOP HELD IN TAIWAN Speakers from the inaugural EDFAS Asia workshop.
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