A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS PAGE 40 2025 WINNERS NOVEMBER 2026 | VOLUME 28 | ISSUE 4 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org HELPING STUDENTS DEFINE PATHS INTO FAILURE ANALYSIS LOW-TEMPERATURE FAILURES IN A TRANSCEIVER TRANSFORMER DRIVER ADVANCED PACKAGING ANALYSIS: UNLEASHING AI’S FULL POTENTIAL 2 12 4 3D IMAGING OF INTEGRATED CIRCUITS VIA LIMITED ANGLE X-RAY TOMOGRAPHY 21
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS PAGE 40 2025 WINNERS NOVEMBER 2026 | VOLUME 28 | ISSUE 4 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org HELPING STUDENTS DEFINE PATHS INTO FAILURE ANALYSIS LOW-TEMPERATURE FAILURES IN A TRANSCEIVER TRANSFORMER DRIVER ADVANCED PACKAGING ANALYSIS: UNLEASHING AI’S FULL POTENTIAL 2 12 4 3D IMAGING OF INTEGRATED CIRCUITS VIA LIMITED ANGLE X-RAY TOMOGRAPHY 21
edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 ABOUT THE COVER See page 40 for a description of the contest images collage on the cover. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS NOVEMBER 2026 | VOLUME 28 | ISSUE 4 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Unveiling Via Sidewall Nanogaps: A Case Study of Low-Temperature Failures in a Transceiver Transformer Driver Angelly Crisar Entice-Gomez This article presents a comprehensive failure analysis of a cold temperature anomaly observed in a customerreturned isolated RS-485 transceiver with an integrated transformer driver. Author Guidelines Author guidelines and a sample article are available at edfas. org. Consult the guidelines prior to manuscript preparation. 4 12 2 GUEST EDITORIAL Marla L. Dowell and Anita Balaraman 3 CALL FOR PAPERS 30 EDFAS AWARDS 31 ASM AWARDS 32 BOARD CANDIDATE PROFILES Felix Beaudoin 37 DIRECTORY OF FA PROVIDERS Rosalinda Ring 39 LITERATURE REVIEW Michael R. Bruce 41 PRODUCT NEWS Ted Kolasa 43 TRAINING CALENDAR Rosalinda Ring 45 GUEST COLUMN 48 ADVERTISERS INDEX 3D Imaging of Integrated Circuits via Limited Angle X-ray Tomography Nathan Nakamura, Jordan Fonseca, Joseph W. Fowler, Felix H. Kim, Zachary H. Levine, John Henry Scott, Paul Szypryt, Andras E. Vladar, and Daniel S. Swetz This work shows 3D images of an integrated circuit at sub-100 nm spatial resolution and discusses key experimental considerations for achieving nanoscale x-ray computed tomography on planar semiconductor devices. 21 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Advanced Packaging Failure Analysis: Unleashing AI’s Full Potential Sam Lin Packaging-related defects have emerged as one of the dominant yield and reliability limiters for advanced AI hardware. The success of the 3DFabric Alliance therefore depends not only on advanced process integration, but also on the ability to rapidly detect, localize, and understand packaging defects across multiple length scales, enabling faster learning cycles, improved yield ramp, and robust field reliability. 12 4 21
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 2 Ask failure analysis engineers how they found their way into the field, and you will hear a tapestry of nonlinear stories. They come from engineering, physical sciences, mathematics, and computer science, with passions for debugging circuits, isolating stress anomalies, or writing code to interpret hardware signals. One of the greatest strengths of electronic failure analysis is that it requires practitioners who can connect across disciplines through physical testing, device behavior, and system-level performance. Certificate programs in failure analysis illustrate the tension of traditional pathways into failure analysis. While these programs help students prepare for careers in failure analysis, they can be confusing for students unfamiliar with industry jargon or unable to visualize the work itself. When certificates are tied to specific degree paths, they implicitly suggest there is a “right” way to enter the field. With anticipated semiconductor workforce shortages, this signaling matters.[1] Students who do not see themselves in prescribed pathways may opt out, even when they already have strong alignment with the underlying analytical and durable skills. After all, you can’t be what you can’t see, and too few students see themselves as failure analysis engineers. Compounding this challenge is the way students experience “failure.” In academic settings, failure is something to avoid. Success is measured through grades and mastery of well-defined problems, encouraging students to select familiar paths where they can perform well rather than explore unfamiliar topics where they might struggle, iterate, and learn. Failure analysis, by contrast, is fundamentally about engaging with failure: systematically, creatively, and constructively. It requires curiosity about what went wrong, persistence through ambiguity, and a willingness to test hypotheses that may not hold. These habits are not easily cultivated in environments that reward only correct answers. To bridge this gap, we need models that make the field more visible, accessible, and aligned with how students discover their interests. EDFASsponsored failure analysis workshops are one approach. Near-peer mentoring programs and career discovery models—such as those piloted through the EDGE-Epixego partnership are another, using a competency-driven framework to identify STEM students who possess the cognitive architecture for failure diagnostics. Near-peer mentors can translate between coursework and professional practice. They help students connect what they already enjoy—puzzles, debugging, writing, experimentation—to the work of failure analysis. A physics student who loves solving complex problems and communication, NOVEMBER 2026 | VOLUME 28 | ISSUE 4 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL REDEFINING PATHWAYS INTO FAILURE ANALYSIS: FROM DEGREES TO DISCOVERY Marla L. Dowell, EDGE Consortium, Dartmouth College marla.dowell@dartmouth.edu Anita Balaraman, Epixego abalaraman@epixego.com edfas.org PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA - nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista MITRE Corp. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Marvell Technology Inc. Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Amrutha Sampath NXP Semiconductors Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2026 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $190 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. (continued on page 47)
FAILURE ANALYSIS OF ULTRA-EFFICIENT ELECTRONICS Abstract submission deadline: April 16, 2027 CALL FOR PAPERS NOW OPEN! OCTOBER 31–NOVEMBER 4, 2027 PHOENIX CONVENTION CENTER, PHOENIX, ARIZONA The U.S. Department of Energy estimates that since the beginning of this decade, energy use from microelectronics alone has expanded to account for over 10% of global electricity use. At the same time, innovations such as cloud infrastructures and AI have triggered an explosion in demand for high power computing and connected devices. The transistor densification realized from low supply voltages and nanometer scale process nodes ironically brings the revenge of Ohm’s law, where the latest AI device packaging is being designed to handle currents into the kiloamp range. This is driving the need to implement next-generation technologies to further improve device efficiency, power delivery, and thermal management and brings fresh challenges to the failure analyst. • Integration of voltage regulation and power management circuitry into the substrate • Co-packaged optics to efficiently increase communication bandwidth • FA of Ultra-Efficient Device Technologies • Emerging FA Techniques and Concepts • Die Level Fault Isolation • Design for Analysis, Test, and Diagnostics • Package Level Fault Isolation • System-in-Package and 3D Devices • Wide Bandgap Power Devices (SiC, GaN, new materials) • AI Applications for Failure Analysis • Boards and Systems • Novel materials for device construction and thermal management • On-chip integrated energy storage • Back-end fabricated devices to extend 3D integration Paper selection is based entirely on information submitted in abstracts and will be evaluated on novelty, completeness, quality, and benefit to the FA community. Abstracts should be a minimum of two pages long, including images and figures. References are required. Original, unpublished abstracts are solicited in the following topic areas: • Sample Preparation and Device Deprocessing • FIB Sample Preparation and Circuit Edit • Microscopy Analysis and Materials Characterization • Device Analysis Case Studies • FA Process and Workflows • Product Yield • Silicon Photonics and Co-Packaged Optics • Trusted Electronics Come to share your experiences and advance the industry and your career at the International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community. We invite you to submit your work for publication and to present it to the community in Phoenix, Arizona, for the 53rd year of ISTFA. • Original, unpublished, and novel material is being solicited on testing, analysis, characterization, and metrology of electronic devices and systems from the nanoscale and upward. • Case studies, review papers, and non-commercial work from vendors are encouraged.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 4 EDFAAO (2026) 4:4-11 1537-0755/$19.00 ©ASM International® ADVANCED PACKAGING FAILURE ANALYSIS: UNLEASHING AI’S FULL POTENTIAL Sam Lin Thermo Fisher Scientific, Hillsboro, Oregon sam.lin@thermofisher.com INTRODUCTION Artificial intelligence (AI) accelerators and high-performance computing (HPC) processors demand extreme memory bandwidth, ultra-low latency, and exceptional power efficiency. These requirements have fundamentally reshaped semiconductor system design, driving the widespread adoption of advanced packaging technologies, particularly 2.5D interposers with high-bandwidth memory (HBM), 3D die stacking, and heterogeneous chiplet integration. As highlighted at the 2022 TSMC Open Innovation Platform (OIP) for its 3DFabric Alliance, the future of AI performance scaling is no longer determined by transistor density alone (Fig. 1).[1] Instead, TSMC’s 3DFabric Alliance defines a tightly integrated ecosystem spanning design, manufacturing, materials, equipment, and testing, with the objective of accelerating innovation while ensuring manufacturability and long-term reliability. In this new paradigm, system-level performance and reliability increasingly depend on the quality and integrity of advanced packaging structures, including microbumps, redistribution layers (RDLs), through-silicon vias (TSVs), and hybrid bonding interfaces. Together, these structures form the critical electrical, thermal, and mechanical pathways that enable massive data transfer between logic and memory, which is essential for AI training and inference workloads. Within this ecosystem, FA and advanced characterization technologies play a foundational role. For AI devices, even a single latent packaging defect, such as a void in a microbump, a discontinuity in an RDL, a TSV defect, or underfill delamination, can result in bandwidth throttling, increased power consumption, thermal instability, or early life failure in the field. As a result, packaging-related de- fects have emerged as one of the dom- inant yield and reliability limiters for advanced AI hardware. The success of the 3DFabric Alliance therefore depends not only on advanced process integration, but also on the ability to rapidly detect, localize, and understand packaging defects across multiple length scales, enabling faster learning cycles, improved yield ramp, and robust field reliability. HOW FAILURE ANALYSIS REVEALS PACKAGING-BURIED DEFECTS Compared with conventional consumer electronics, AI accelerators and HPC devices operate under significantly more aggressive electrical, thermal, and mechanical conditions, which fundamentally changes the nature of packaging-related failures. Key stress factors include: • Higher current densities in microbumps and RDLs, accelerating electromigration and void formation. • Sustained high power dissipation, which amplifies thermomechanical stress, package warpage, and interfacial fatigue. • Tight timing margins, making AI devices highly sensitive to even minor signal and power integrity degradation. • Large package form factors (e.g., HBM-based accelerators), increasing the risk of underfill delamination, die cracking, and interposer fracture. Fig. 1 TSMC 3DFabric Alliance announced at the Open Innovation Platform Ecosystem Forum 2022.
edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 As a result, advanced packaging defects in AI systems are not only more frequent, but also more complex and multi-modal, often involving coupled electrical, thermal, and mechanical failure mechanisms. Typical buried defect locations include microbumps, RDLs, TSVs, hybrid bonding interfaces, underfill layers, and die-to-interposer interfaces, all of which are inaccessible to conventional surface inspection. FAILURE ANALYSIS REQUIREMENTS FOR ADVANCED AI PACKAGING To effectively address these challenges, modern FA must deliver three core capabilities: (1) Early localization of buried defects without destroying high-value AI devices; (2) Micro- to nanoscale root-cause identification across metals, dielectrics, and heterogeneous interfaces; and (3) Data-driven feedback to design, materials, and process teams to accelerate yield learning and reliability improvement. Meeting these requirements demands a systematic and specialized FA workflow, which can be broadly divided into nondestructive FA and destructive FA. NONDESTRUCTIVE FA: LOCALIZING BURIED DEFECTS Nondestructive FA techniques are indispensable for advanced AI hardware due to high device cost, limited sample availability, and the complexity of 2.5D/3D package architectures. These methods are typically applied first to preserve sample integrity while enabling rapid identification of regions of interest for deeper analysis. Scanning acoustic microscopy (SAM) operates in three primary modes, A-scan, B-scan, and C-scan, each providing different types of information about a sample.[2-5] The A-scan captures the raw ultrasonic waveform, recording echo amplitude as a function of transit time, and is typically used to optimize inspection conditions by max- imizing signal amplitude at a specific point of interest. Building on this, the B-scan generates a cross-sectional view of the material, offering depthresolved information that reveals inter- nal structures along a vertical slice. In contrast, the C-scan produces a planar image at a selected depth, effectively mapping features across a specific layer within the sample. For both B-scan and C-scan modes, proper transducer positioning and signal tuning are essen- tial to ensure that reflections from the region of interest are captured with sufficient intensity for accurate imaging. Therefore, the C-scan mode (commonly referred to as C-SAM) is particularly effective for detecting delamination, voids, and cracks at material interfaces, such as underfill-to-die, mold-to-substrate, and interposer layers, and serves as one of the key FA methods in advanced packaging. These defects represent major reliability risks in large-format AI packages, particularly under high thermal and mechanical stress. Figure 2 displays extensive delamination at the die-attach level. A gated planar C-SAM image at the underlayer level shows that the delamination is widespread, with layers in the substrate gradually separating. The rectangular defect pattern at the bottom right indicates a popcorn crack resulting from the sudden expansion of trapped moisture.[5] X-ray computed tomography (XCT: micro-CT and nano-CT).[6-8] A fast overview scan (~30 s) at micrometerscale voxel size is first performed to capture the full structure of the sample, enabling rapid navigation and identification of regions of interest (ROIs), despite some noise and under-sampling artifacts. Based on this, a targeted high-resolution nano-CT scan is conducted on a selected ROI, achieving a voxel size on the order of a few hundred nanometers. This higher-resolution scan provides sufficient data quality for detailed analysis, including the identification of sub-micron voids in bump bonds. Figure 3 demonstrates that XCT provides 3D visualization of internal package structures, including TSVs, microbumps, solder joints, and voids. XCT enables rapid, package-level defect screening and precise localization of buried anomalies, such as voids in microbumps, cracks in RDLs, and TSV defects, without physical cross-sectioning. Fig. 2 C-SAM scanned top layer and underlayer images indicating the extensive delamination between the die surface and the mold compound.[5]
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 6 Based on inspection needs, users can balance factors such as time-to-data (urgency), required data precision, and the level of structural detail, and accordingly select the appropriate imaging condition, ranging from fast micro-CT for quick screening to high-resolution nano-CT for detailed analysis. Electrical fault isolation (e.g., lock-in thermography, emission microscopy).[9-11] Lock-in thermography identifies electrically active defects under realistic operating conditions, including electromigration hotspots, resistive shorts, leakage paths, and high-resistance inter- connects that directly impact performance and power efficiency. The technique operates by applying a periodic electrical stimulus to a device under test, generating localized heating at defect sites due to Joule heating. An infrared camera synchronously detects the resulting temperature modulation, and lock-in signal processing extracts phase and amplitude information to enhance weak thermal signals while suppressing noise. This enables high-sensitivity localization of electrically active defects in both lateral and axial (depth) directions within complex advanced packaging structures. Enhanced LIT analysis of a defect in a 4-layer HBM stack along lateral direction is shown in Fig. 4. The right side shows the raw amplitude response at 21 Hz, where heat diffusion causes significant spreading, limiting precise localization. The left image of Fig. 4 demonstrates improved lateral localization using phase-based heat propagation inversion, reducing the apparent hotspot size by over an order of magnitude. Engineers can first judge the true lateral defect position from the image plane. Furthermore, Fig. 5 shows enhanced LIT analysis of a defect in a four-layer HBM stack along axial direction. The right image of Fig. 5 presents a reconstructed thermal cross-section, enabling quantitative depth estimation of the defect at approximately 670 µm below the surface. The data in this graph are synthesized through recursive extrapolation for inverting the heat propagation under consideration of the sample’s internal structure, the corresponding thermal diffusion coefficients, and the phase distribution measured across the sample’s surface. From this graph, the depth of the hot spot can be approximated to be 670 µm underneath the sample’s surface. The left Fig. 3 A reconstructed vertical slice and 3D render of the region of interest scan of HBM device obtained by high-resolution x-ray nano-CT.[6] Fig. 4 Comparison of before (right) and after (left) results of lateral-resolution-enhanced LIT 3D localization of a defect in a 4-layer HBM device.[10]
edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 image of Fig. 5 contains a scanning electron micrograph of the physical cross-section of the sample. Summation of the thicknesses of the individual layers leads to a defect depth of 665 µm. Despite the higher structural complexity of the sample, both lateral and axial localization were considerably accurate when conducting the additional recursive inversion-based analysis of the heat propagation. The achievable precision will however depend on how close the closest reconstruction plane is located with respect to the actual source depth and thus also depend on the increments of the recursive reconstruction sequence. By combining SAM, XCT, and LIT techniques, FA engineers can identify failure sites with high confidence before any destructive steps are taken. This integrated nondestructive approach significantly reduces analysis cycle time, protects high-value AI devices, and ensures that subsequent high-resolution destructive FA is both targeted and efficient. DESTRUCTIVE FA: ROOT-CAUSE IDENTIFICATION After defect regions are localized through nondestructive analysis, destructive FA techniques provide the spatial resolution and material contrast required for definitive root-cause identification in advanced AI packaging. DualBeam focused ion beam-scanning electron microscopy (FIB-SEM) has become an indispensable tool in both materials science and semiconductor failure analysis due to its unique ability to combine site-specific material removal with high-resolution imaging.[12-16] This capability enables precise cross-sectioning, 3D structural characterization, and direct correlation between physical defects and functional performance, which is critical for understanding increasingly complex device architectures and advanced packaging technologies. Different FIB ion sources are best suited for varying sample sizes and technology requirements. Ga+ FIB excels in high-precision, small-volume applications, such as TEM sample preparation and detailed analysis of logic and memory devices, typically at the 40 µm3 scale. Plasma FIB (PFIB) extends this capability to larger volumes from 200 to 500 µm3, making it well-suited for CMOS, advanced packaging, and power semiconductor analysis, including tasks such as delayering and diagonal milling while maintaining good resolution. For even larger-scale investigations, femtosecond (fs)-laser-assisted PFIB enables above millimeter-scale material removal with high throughput, providing rapid access to deeply buried features in complex 3D structures. Figure 6 demonstrates the use of the Thermo Scientific Helios 5 Laser PFIB triple-beam system to address the complexities of a 4H AMD Radeon VII HBM2 device. The fs laser enables rapid material removal on the order of 1 mm³ (Figs. 6a and 6b), while Xe+ plasma rocking polishing minimizes curtaining effects (Fig. 6c). This polishing step effectively flattens surface artifacts induced by vertically aligned TSV pillars and microbumps following fs-laser ablation. High-resolution SEM images (Fig. 6d) are then acquired and processed using automated iFast software to generate 2D metrology measurements, such as microbump and TSV dimensions, as well as stacking offset (Figs. 6e and 6f). This system is particularly well suited for failure Fig. 5 Axial defect localization in 4H HBM.[10] Left: Electron micrograph of the sample’s physical cross-section. The red marker indicates the location of the I/O diode used for thermal stimulation. The thermal source is located at a depth of 665 µm inside the sample. Right: Cross-sectional view through the sample’s synthetically computed heat source distribution. The thermal wave converged at a depth of 670 µm, only 5 µm lower than the depth estimated from the electron micrograph. The red dashed line is the actual source depth obtained from the electron micrographs. The estimated source depth is indicated by the solid red line.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 8 analysis of advanced packaging devices. These structures contain deeply buried interconnects and interfaces—such as microbumps, RDLs, TSVs, and hybrid bonding interfaces—that are critical to device performance and reliability. The system enables efficient exposure and high-resolution inspection of these regions, allowing identification of defects such as voids, cracks, interfacial delamination, and metallurgical degradation, all of which directly impact electrical and mechanical integrity. Transmission electron microscopy (TEM) delivers nanoscale to atomic-scale insight into microstructural and chemical phenomena, such as intermetallic compound (IMC) formation, atomic diffusion, electromigration damage, crack initiation, and bonding quality.[17-22] It is essential for understanding long-term reliability risks under the sustained electrical and thermal loads typical of AI workloads. Figure 7 presents the characterization of a low-melting-point high-entropy alloy (HEA) solder, synthesized by melting equimolar amounts of In, Zn, Sn, and Bi into ingots, followed by deformation into 100 µm-thick solder foils.[22] IMC formation at the solder/Cu interface was investigated using the Thermo Scientific Helios 5 UC DualBeam system and the Thermo Scientific Talos F200X TEM. Microstructural and elemental analyses reveal the formation of a dual-layer IMC structure at the interface, consisting of Cu5Zn8 phases. TEM imaging shows that the IMC layer comprises two distinct sub-layers. Selected area diffraction patterns, compared with single-crystal spots and polycrystalline rings and referenced against the PDF database, confirm that both sub-layers correspond to Cu5Zn8. However, EDS point and line analyses indicate compositional differences: The sub-layer adjacent to the Cu substrate is composed of pure Cu5Zn8, whereas the sub-layer near the solder contains Cu5Zn8 mixed with Sn, Bi, and In. The activation energy for IMC formation was determined to be 35.67 ± 3.4 kJ/mol. These results demonstrate that TEM enables nanoscale phase identification, compositional mapping, and atomic-level structural analysis of IMC layers, providing critical insight into interfacial reactions and reliability mechanisms in HEA solder joints. Together, these destructive FA techniques transform abstract reliability concerns into concrete physical failure mechanisms that engineers can directly address. By enabling fast learning cycles, accelerated yield ramp, and robust reliability qualification, FIB/SEM and TEM play a critical role in ensuring that advanced AI systems meet the stringent requirements of hyperscale and data- center deployments. (a) (b) (c) (d) (e) (f) Fig. 6 High-resolution SEM images were captured after the Helios 5 Laser PFIB cross-sectioning process. (a) and (b) show the microbump array structure after the laser ablation process; (c) presents the Xe+ plasma polished cut face, revealing a clean and clear sandwiched Cu-Sn-Cu microbump and the stacked DRAM; (d) is a high-resolution SEM image of a single microbump; (e) and (f) are automatic metrological images used to measure each microbump offset, TSV width, and height.[16]
edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 FAILURE ANALYSIS AS A PILLAR OF ADVANCED PACKAGING INNOVATION As illustrated in Fig. 8, modern failure analysis spans an exceptionally wide range of length scales and semiconductor value chain coverages and forms a comprehensive, multi-modal toolkit that supports every stage of semiconductor development, from raw materials to advanced packaging. Rather than relying on a single technique, today’s FA approach is inherently layered and integrated, with each method contributing complementary insights to address the growing complexity of 2.5D and 3D device architectures. Across the semiconductor value chain, these FA technologies provide critical benefits. At the package and system level, SAM and x-ray micro/ nano-CT enable rapid, nondestructive detection of buried defects such as delamination, voids, and cracks within mold compounds, underfill, and interposer structures. Bridging physical inspection with functional performance, electrical fault isolation techniques such as ELITE (lock-in thermography) localize electrically active defects, including leakage paths, resistive shorts, and electromigration hotspots, under realistic operating conditions. After areas of interest are identified, site-specific cross-sectioning using DualBeam FIB-SEM enables high-resolution structural and compositional analysis, while TEM provides atomic-level insight Fig. 7 TEM and EDS results of IMC: (a-1) HRTEM image of point A; (a-2) diffraction pattern of point A; (a-3) EDS of point A; (b-1) HRTEM image of point B; (b-2) diffraction pattern of point B; (c) diffraction pattern of point C; (d-1) diffraction pattern of point D; (d-2) HRTEM image of point D; (d-3) EDS of point D; (e) diffraction pattern of point E; (f) EDS mapping results of IMC layer; and (g) EDS line result of IMC.[22] Fig. 8 Multiscale coverage of advanced FA technologies across the semiconductor value chain, from raw materials and wafer-level defect localization to singledie and advanced packaging.[5,6,10,16,22] (b-1) (b-2) (d-1) (d-2) (a-1) (a-2) (d-3) (a-3) (c) (e) (f) (g)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 10 into interfacial phenomena, including intermetallic compound formation, diffusion behavior, bonding quality, and interface integrity. Together, these technologies establish a closed-loop FA workflow that transforms hidden defects into actionable knowledge, accelerating root-cause identification and process optimization. This capability is increasingly vital as advanced packaging becomes a central driver of system performance. By enabling deeper understanding of failure mechanisms in critical structures, such as microbumps, RDLs, TSVs, and hybrid bonding interfaces, FA directly supports improvements in reliability, yield, and design robustness. In the context of AI innovation, where performance, power efficiency, and bandwidth are tightly coupled to packaging integrity, advanced FA is no longer just a diagnostic tool but a strategic enabler. It empowers semiconductor manufacturers to de-risk new architectures, shorten development cycles, and sustain scaling beyond traditional limits—ultimately accelerating the growth of next-generation AI systems and the broader semiconductor ecosystem. FAILURE ANALYSIS AND ESD/ COMPLIANCE AS FINAL GATES FOR AI PRODUCT LAUNCH Even when advanced packaging structures are correctly assembled and free of detectable physical defects, AI hardware is not necessarily ready for deployment. AI accelerators operate at unprecedented power density, signal speed, and system complexity, creating conditions where electrostatic discharge (ESD) and system-level compliance issues can become catastrophic latent failure mechanisms.[23,24] Accumulated charge across large AI boards, interposers, and high-speed interfaces can discharge suddenly, overwhelming protection structures and damaging entire systems, particularly during handling, integration, and early deployment. While ESD and compliance test solutions (CTS) are not failure analysis techniques in the traditional sense, they serve as a critical final validation layer that complements FA by ensuring electrical robustness prior to product release. Whereas FA verifies structural integrity and identifies root-cause physical defects, CTS confirms that AI systems meet industry, customer, and regulatory requirements under real-world electrical stress conditions. Specifically, CTS evaluates: • ESD robustness at board, module, and system levels • Signal and power integrity compliance across highspeed interfaces • Electromagnetic compatibility (EMC) and noise margins in dense AI platforms • System-level resilience during manufacturing, handling, and deployment Without proper ESD and CTS qualification, even a defect-free advanced package remains vulnerable to latent compliance failures, unpredictable field behavior, and costly data-center incidents. In the AI era, FA is no longer a reactive troubleshooting activity, it is a strategic enabler that directly improves yield of complex 2.5D and 3D advanced packages, reduces field failure risk in hyperscale data-center environments, enables aggressive power, bandwidth, and performance scaling, and shortens learning cycles for new packaging and integration technologies. When combined with ESD/CTS, modern FA frameworks provide a complete AI product readiness assessment, ensuring that systems are not only manufacturable, but also compliant, robust, and deployment-ready. By breaking down advanced packaging and system-level compliance risks with unprecedented resolution and speed, FA and CTS together empower the semiconductor industry to deliver reliable, high-performance AI platforms at scale. SUMMARY As advanced packaging increasingly defines the performance limits of AI hardware, failure analysis has emerged as a critical driver of both innovation and risk mitigation. No longer a support function, FA is now a foundational pillar of the AI hardware ecosystem, enabling complex packaging technologies to move confidently from development into high-volume production. By integrating nondestructive defect localization, nanoscale root-cause characterization, and system-level compliance validation, FA transforms hidden reliability risks into actionable insight and ensures field-ready AI platforms. As AI systems continue to scale in complexity, power density, and integration, the strategic importance of failure analysis will only continue to grow. REFERENCES 1. TSMC Introduces the Newest Addition to OIP: The 3DFabric Alliance. Taiwan Semiconductor Manufacturing Company Limited, p. 2022. 2. P.M. Zadeh, S. Brand, and E. Dehghan-Niri: “Recent Progress in Structural Integrity Evaluation of Microelectronic Packaging using Scanning Acoustic Microscopy (SAM): A Review,” Sensors, 25(24), 2025, p. 7499. 3. S. Brand, et al.: “Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications,” J Mater Sci: Mater Electron, 22, 2011, p. 1580-1593.
edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 ABOUT THE AUTHOR Dr. Sam Lin is the regional marketing manager for Thermo Fisher Scientific, responsible for the semiconductor microscopy, advanced benchmarking, and failure analysis business across the Asia-Pacific and Japan (APJ) region. Lin received his Ph.D. in materials science and engineering from National Tsing Hua University, Taiwan. He began his career at FEI, later Thermo Fisher Scientific, and subsequently served as technical manager at BESI, leading hybrid bonding technology deployment in Taiwan and supporting technology introduction, process development, pre-sales, system implementation, and customer engagement. Since rejoining Thermo Fisher Scientific in 2022, he has leveraged his technical expertise together with strategic marketing leadership to help customers address increasingly complex semiconductor challenges through advanced benchmarking, failure analysis, and process characterization solutions. 4. S. Brand, et al.: “Non-destructive Wafer-level Bond Defect Identification by Scanning Acoustic Microscopy,” Microsyst Technol, 21, 2015, p. 1385-1394. 5. H. Yu: “Scanning Acoustic Microscopy for Material Evaluation,” Appl. Microsc., 50(25), 2020. 6. T. Dreier, D. Nilsson, and J. Hållstedt: “Fast and High-resolution X-ray Nano Tomography for Failure Analysis in Advanced Packaging,” Microelectronics Reliability, 168, 2025, p. 115694. 7. D-P. Tran, et al.: “Non-destructive Micro Analysis of Electromigration Failures in Solder Microbumps using 3D X-ray Computed Tomography,” Materials Characterization, 194, 2022, p. 112404. 8. P. Roumanille, et al.: “Using X-ray Imaging for the Study of Crack Development in Solder Reliability Testing,” Microelectronics Reliability, 149, 2023, p. 115079. 9. M. Mousnier, et al.: “Lock-in Thermography for Defect Localization and Thermal Characterization for Space Application,” Microelectronics Reliability, 88-90, 2018, p. 1021-1026. 10. S. Brand, et al.: “Localization Enhancement in Quantitative Thermal Lock-in Analysis using Spatial Phase Evaluation,” Microelectronics Reliability, 168, 2025, p. 115703. 11. A.M.R. Sharma, et al.: “Enhanced Infrared Imaging for Die-Level Fault Isolation using Lock-In Thermography,” Journal of Failure Analysis and Prevention, 24(9), 2024, p. 2129-2141. 12. H. Yang, et al.: “Brittle-to-ductile Transition of Au₂Al and AuAl₂ Intermetallic Compounds in Wire Bonding,” Journal of Materials Science: Materials in Electronics, 2018. 13. T.-F. Lu, P.-Y. Lee, and Y.S. Wu: “Effect of Compressive Stress on Cop- per Bonding Quality and Bonding Mechanisms in Advanced Packaging,” Materials, 17, 2024, p. 2236. 14. S.-C. Yang, Y.-T. Yang, and C. Chen: “Electromigration in Cu–Cu Joints: Measurement of Activation Energy and Polarity Effect,” Microelectronics Reliability, 33, 2024, p. 4522-4532. 15. T.-F. Lu, et al.: “Enhanced Copper Bonding Interfaces by Quenching to Form Wrinkled Surfaces,” Nanomaterials, 14(10), 2024, p. 861. 16. H. Lin, et al.: “Comprehensive Analysis of High-bandwidth Memory (HBM) with Helios 5 Laser PFIB: Integrating 2D High-resolution SEM Imaging and 3D Metrology,” NANOTS 2025. 17. C. Yang, et al.: “Effect of Sn Surface Diffusion on Growth Behaviors of IMCs in Cu/Ni/SnAg Microbumps,” Materials Characterization, 158, 2019, p. 109964. 18. C.-W. Kao, et al.: “Highly Robust Ti Adhesion Layer During Terminal Reaction in Micro-bumps,” Materials, 15, 2022, p. 4297. 19. Y.K. Lee, et al.: “Grain Modification and Formation of Tough IMC Phase in Submicron Sn–Ag Microbumps via Doping Zn and Ni in Cu Substrate,” Vacuum, 217, 2023, p. 112531. 20. C. Li, et al.: “Fe Content-dependent Non-monotonic IMC Growth Kinetics in Co–Fe Alloy Barrier Microbumps,” Materials Today Communications, 42, 2025, p. 109230. 21. C. Li, et al.: “Co–W Alloy as an Effective Barrier Layer for Suppressing Sn Surface Diffusion and Sidewall IMCs in Small-size Micro-bumps,” Journal of Alloys and Compounds, 948, 2025, p. 170825. 22. W. Guodong, et al.: “Microstructure and Mechanical Properties of Cu/In–Zn–Sn–Bi/Cu Joints Bonded with High-entropy Alloy Solder at Ultra-low Temperature,” Journal of Materials Science: Materials in Electronics, 36, 2025, p. 926. 23. X. Chen, et al.: “An ESD Robust High Holding Voltage Dual-direction SCR with Symmetrical I-V Curve by Inserting a Floating P+ in PWell,” Solid-State Electronics, 160, 2019, p. 107627. 24. S.-C. Huang, et al.: “Improving ESD Protection of 5 V NMOSFET Large Array Device in 0.4 µm BCD Process,” Microelectronics Reliability, 84, 2018, p. 48-54. Advertise in Electronic Device Failure Analysis magazine! For information about advertising in Electronic Device Failure Analysis: KJ Johanns, Business Development Manager 440.671.3851, kj.johanns@asminternational.org Current rate card may be viewed online at asminternational.org/advertise.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 12 UNVEILING VIA SIDEWALL NANOGAPS: A CASE STUDY OF LOW-TEMPERATURE FAILURES IN A TRANSCEIVER TRANSFORMER DRIVER Angelly Crisar Entice-Gomez Analog Devices Inc. angelly.entice@analog.com EDFAAO (2026) 4:12-20 1537-0755/$19.00 ©ASM International® INTRODUCTION Cold failures are challenging to analyze due to their intermittent or non-reproducible nature, often resulting in inconclusive findings and an unidentified failure mechanism. Unlike catastrophic failures with obvious physical damage, cold failures often leave minimal or no trace, making root cause identification through standard inspection difficult. This article presents a comprehensive failure analysis of a cold temperature anomaly observed in a customer-returned isolated RS-485 transceiver with an integrated transformer driver. Various techniques including backside analysis were effectively employed under controlled conditions to preserve the failure state while performing the fault isolation and facilitating root cause identification. The investigation highlights the critical role of using low acceleration voltage in scanning electron microscopy (SEM) for detecting nanoscale defects, which enabled the identification of a subtle open via anomaly causing the failure. The study underscores the importance of coherent and correlated data in enabling confident decision-making, ultimately leading to successful failure resolution and preventing the mechanism from remaining unidentified. In isolated transceivers, a transformer driver is the internal block that generates a high‑frequency AC signal used to transfer power or data across an on‑chip micro‑ transformer. Because transformers cannot pass DC, the driver converts regulated DC into a high‑frequency waveform that can pass through the isolation barrier. A customerreturned isolated RS-485 transceiver with an integrated transformer driver unit was reported to have no oscillation on the transformer driver at low temperatures (~5°C). Automatic test equipment (ATE) testing confirmed that the unit was failing the transformer driver oscillator frequency parameter test at cold temperatures. During bench testing, the unit showed no oscillation on the transformer drivers (D1 and D2). In addition, a significant decrease in the supply current was observed when the unit was exposed to cold temperatures before power up. Interestingly, the unit eventually recovered and began to oscillate and draw normal supply current once the temperature increased to ambient levels after power up. Additionally, the failure only manifests when the unit is subjected to cold temperatures prior to power up. However, if the unit is powered up at ambient temperature and then exposed to cold temperatures, it functions normally. See Figs. 1 to 3. DIE BACKSIDE FAULT ISOLATION AND CHALLENGES ENCOUNTERED An extensive failure analysis was conducted to identify the mechanism of the failure. The analysis focuses on the transformer driver die of the unit. To achieve a cold environment, a cold spray was applied to the unit to rapidly lower its temperature. However, maintaining a constant failing temperature proved challenging, as the rapid cooling effect of the spray does not provide sustained temperature control. After the temperature reached ambient levels, the part recovered and the failure could no longer be observed. Thus, proper timing was crucial to isolate the failure effectively. Fig. 1 IDD supply current test of the returned unit at ambient and cold temperatures.
edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 Fig. 2 Oscilloscope plots of the customer-returned unit (CRU) showing the failing cold temperature condition. Fig. 3 Oscilloscope plots of the customer-returned unit (CRU) showing the passing cold temperature condition. Additionally, cold testing can cause moisture to form through condensation, which may result in electrical leakage, corrosion, or false signal readings. These effects can damage the unit or mask the actual fault signatures. With this, die backside analysis using light emission microscopy (LEM) and optical beam induced resistance change (OBIRCH) was performed under controlled cold temperature conditions to minimize moisture-related interference. Die backside analysis is a failure analysis technique in semiconductor engineering where the silicon substrate from the side opposite the active circuitry is accessed to inspect for electrical defects such as opens, shorts, leakage paths, or abnormal device behavior, all while preserving the integrity of the top side metal layers. LEM AND OBIRCH OBSERVATIONS LEM analysis—which identifies electrically active regions by capturing low level infrared emissions—showed an absence of normal emissions on some circuit blocks responsible for oscillation in the internal circuitry of the transformer driver die, indicating that these blocks were unpowered. During OBIRCH analysis—a laser‑based technique that detects resistance changes caused by localized heating to pinpoint opens or high‑resistance defects—fluctuations in the power supply during temperature changes (from cold to ambient temperatures) may have affected the accuracy of the resistance measurements, leading
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 14 to a recurring equipment error that made fault isolation challenging. To address this, various OBIRCH settings and bench setups were explored. The lowest possible voltage setting, where the failure could still be observed, was used while performing the fastest OBIRCH scan mode to capture the failure before the temperature returned to ambient levels. Fortunately, an anomalous resistance change was observed on the unit (Fig. 4). Fig. 4 Fault isolation results of the returned unit at cold temperatures. Fig. 5 Transformer driver die layout and bias circuitry schematics showing the suspected anomalous site.
edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 4 FAULT LOCALIZATION THROUGH SCHEMATICS AND LAYOUT REVIEW AND MICROPROBING ANALYSIS The schematic and layout were reviewed to map the suspected component with respect to its circuit block, functionality, and electrical response. Review revealed that the unpowered circuit blocks during LEM analysis were identified as the oscillator driver circuitry and the reference circuitry. Meanwhile, the circuit block exhibit- ing a resistance change during OBIRCH analysis was identified as the Ibias circuitry. Further review indicated that the anomaly is highly likely on a resistor R1 in the start-up circuitry within the Ibias circuitry block of the transformer driver die of the unit. The anomaly on the resistor R1 may be causing the start-up current to decrease when the unit is subjected to cold temperature prior to power up—making the start-up current insufficient to establish the bias circuitry. The unestablished bias circuitry would cause the other circuit blocks to be unpowered causing no oscillation on the transformer drivers. Microprobe analysis—a technique that uses fine‑pitch electrical probes to directly contact specific nodes on the die to measure voltages, currents, or resistances during active biasing—was performed on the Ibias circuitry of the transformer‑driver die to validate the suspected anomaly at resistor R1. The results revealed that the suspected resistor R1 exhibited a significantly higher resistance than its expected design value, indicating an open‑resistance condition. See Fig. 5. VIA SIDEWALL NANOGAPS UNVEILED Focused ion beam (FIB) uses a finely focused ion beam to mill and expose precise cross-sections of the die. FIB was performed on multiple contacts and vias connected to the suspected resistor R1, and the resulting sections were inspected through SEM, which uses a focused beam of high energy electrons to generate high resolution surface and cross-sectional images. Results did not reveal any significant anomaly initially. Further FIB-SEM inspection was requested to retake the images with a higher magnification on the area of interest (AOI), focusing on the interface of the vias and metals to check for any anomalies. Additionally, it was requested that the images be taken using a lower acceleration voltage at SEM, as the initial FIB cross-section images were observed to have been taken at a higher acceleration voltage. Using lower acceleration voltage at FIB-SEM, results showed nanogaps on the sidewall of the vias connecting the suspected resistor R1 and VDD (Figs. 6 and 7). Fig. 6 Images showing the area of interest (AOI) sites at FIB. (continued on page 18)
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO.4 18 Examination using transmission electron microscopy (TEM)—an analytical technique in which a high‑energy electron beam is transmitted through an ultrathin sam- ple to obtain nanometer‑scale structural and material information—revealed abnormal thin layers along both the left and right sidewalls of the via. Through energy- dispersive x-ray spectroscopy (EDS) analysis, a thin carbon- rich (C-rich) layer within the titanium/titanium nitride (TiN) barrier layer, specifically between the Ti and TiN layers was discovered. Additionally, the analysis showed an oxygen-rich presence across the Ti barrier layer (Fig. 8). ACCELERATING VOLTAGE IN SEM IMAGING Accelerating voltage refers to the potential difference that accelerates electrons from the electron gun down the column and toward the sample in an SEM. Adjusting the accelerating voltage is a critical consideration in SEM imaging as it influences the electron beam interaction volume within the sample. The higher the accelerating voltage, the larger the interaction volume, and the greater amount of signal generation. Higher signal levels improve the signal-to-noise ratio in an image, which allows higher quality images or elemental data to be acquired faster through EDS. However, working at these high accelerating voltages has consequences that can obscure the results of SEM analysis. Increasing the size of the interaction volume means that more signals will be generated from within the subsurface of the sample compared to signals confined to the surface. This can be problematic when trying to analyze small or shallow features. A high-kV image may result in these shallow features becoming transpar- ent or completely invisible due to the stronger signal from the subsurface dominating the image. Using lower accel- erating voltages when imaging the samples can help to prevent these outcomes. Lower accelerating voltages limit electron penetration to the near-surface region, which is advantageous for observing fine surface details and delicate samples that may be damaged by higher energies. Sampling a shallower volume of interaction can increase the visibility of surface features and improve the spatial resolution of the SEM image. The nanogaps on the sidewalls of the anomalous vias were initially not observed using the higher acceleration Fig. 7 FIB cross-section images showing the nanogaps with respect to a correlation unit. UNVEILING VIA SIDEWALL NANOGAPS: A CASE STUDY (continued from page 15)
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