A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2026 | VOLUME 28 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org ELECTRICAL FAULT LOCALIZATION OF INTERCONNECT VIA CHAINS FAILURE ANALYSIS ROADMAP: DIE-LEVEL COUNCIL UPDATE ADVANCED FAULT ISOLATION OF USB2 ESD FAILURES INSPECTION AND METROLOGY CHALLENGES IN HYBRID BONDING 4 28 12 32
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A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2026 | VOLUME 28 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org ELECTRICAL FAULT LOCALIZATION OF INTERCONNECT VIA CHAINS FAILURE ANALYSIS ROADMAP: DIE-LEVEL COUNCIL UPDATE ADVANCED FAULT ISOLATION OF USB2 ESD FAILURES INSPECTION AND METROLOGY CHALLENGES IN HYBRID BONDING 4 28 12 32
edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 ABOUT THE COVER Microscopic Marvel: Dendritic crystal growth. A mesmerizing electron microscope image captures the intricate beauty of branched, tree-like crystalline formations. Photo by Maricel S. Capili, Analog Devices Inc., First Place Winner in Black and White Images, 2025 EDFAS Photo Contest. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2026 | VOLUME 28 | ISSUE 2 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Inspection and Metrology Challenges in Hybrid Bonding Himanandhan Reddy Kottur, Pavanbabu Arjunamahanthi, Liton Kumar Biswas, Istiaq Firoz Shiam, Katayoon Yahyaei, and Navid Asadizanjani This article outlines existing bottlenecks and proposes a pathway toward scalable and adaptive inspection methodologies suitable for next-generation chiplet-based integration. Author Guidelines Author guidelines and a sample article are available at edfas.org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 12 2 GUEST EDITORIAL Keith Serrels 25 ISTFA EXHIBITORS LIST 41 2026 PHOTO CONTEST 42 2026 VIDEO CONTEST 43 PRODUCT NEWS Ted Kolasa 46 DIRECTORY OF FA PROVIDERS Rosalinda Ring 48 LITERATURE REVIEW Michael R. Bruce 50 TRAINING CALENDAR Rosalinda Ring 52 ADVERTISERS INDEX International Roadmap for Failure Analysis: Die-Level Roadmap Council Kristofor Dickson and Venkat-Krishnan Ravikumar An update from the Die-Level Roadmap Council identifies six critical domains for innovation in electrical fault isolation over the next five years. 28 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Electrical Fault Localization of HighDensity 3D Interconnect Via Chains Through Innovative Sample Preparation Kristof J.P. Jacobs A novel approach is introduced that expands the applicability of optical-microscopy-based FA techniques, in- cluding LICA and OBIRCH, to increasingly downscaled device structures. 12 4 32 From System Zap to Silicon Improvement: Advanced Fault Isolation of USB2 Electrostatic Discharge Failures Omkar Rajesh Kachare This article presents a technical evaluation of a universal serial bus (USB2) interface failure within a platform controller hub following a system-level electrostatic discharge event. 32
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 2 When the International Roadmap for Failure Analysis (IRFA) was launched in 2019, the goal was not only to address the existing technological challenges faced by our community, but also to incorporate a forward-looking perspective. As such, a dedicated FA Future Council was established alongside the main Die-Level Roadmap and Package-Level Roadmap Councils. Yet, as time passed and the community began to embrace these efforts, what became clear was a need for us to not only look ahead to the technical challenges but to also consider the awareness challenges our community faced. EDFAS has traditionally worked with a focused understanding and respect for its own workflows. So when the IRFA leadership team began interacting with stakeholders from the wider semiconductor ecosystem—especially those connected to funding prospects—it felt like there was a language barrier between us. What the FA community took for granted, in terms of techniques we commonly use, intricacies of our work, and the value that it brings, was lost on various individ- uals and technology groups who held key positions of influence outside of FA. This, in a way, did not come as too much of a surprise, to be honest. Those of us who have been in FA for long enough have heard of and experienced many situations in which the powerhouse semiconductor industry has treated us as an afterthought or an expensive insurance policy. A service that is called on to save the day when first silicon hits or a new product introduction qualification fails brings all hands to the pump. This has always been the case, and, for some, it was reluctantly accepted. But with the introduction of the IRFA and its fresh energy, it was decided that a formal attempt should be made to try to correct it. The Failure Analysis Outreach Council (FAOC) comprises a selection of dedicated tool users, tool vendors, and academics from across the FA community who have been tasked with three main objectives: Capitalize on the solid gaps identified by each IRFA Council to generate more FA awareness/engagements across the broader semiconductor ecosystem to ensure FA needs are understood and accounted for. This will be used directly to drive active engagement with CHIPS Act initiatives in the U.S. such as NIST Metrology and the National Semiconductor Technology Center (NSTC), so we can stay up to date on the latest developments and communicate them to the FA community. Part of this effort also concerned promoting the idea of establishing an FA Center of Excellence. Network and collaborate with industry bodies, conferences, workshops, and initiatives, etc. This will be used to bring FA gaps and needs directly into design and process R&D communities, especially as transistor MAY 2026 | VOLUME 28 | ISSUE 2 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL FAILURE ANALYSIS OUTREACH COUNCIL: AWARENESS, EDUCATION, INFLUENCE Keith Serrels, Hamamatsu kserrels@hamamatsu.com edfas.org (continued on page 40) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2026 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $190 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Serrels
edfas.org 3 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 DESIGN FOR ANALYSIS To learn more and find registration details, visit: REGISTRATION OPENS THIS SUMMER! OCTOBER 4–8, 2026 HENRY B. GONZALEZ CONVENTION CENTER, SAN ANTONIO, TEXAS Join us for the 52nd International Symposium for Testing and Failure Analysis (ISTFA), which is set to take place in San Antonio, Texas, from October 4-8, 2026. As the premier event for the microelectronics failure analysis community, ISTFA brings together leading experts, industry professionals, and researchers to share insights, innovations, and methodologies in the field. Attendees will engage in a comprehensive program that includes keynote presentations, technical sessions, workshops, and networking opportunities, all designed to foster collaboration and knowledge exchange. Topics will include: WHAT TO EXPECT AT ISTFA 2026 • AI Applications for Failure Analysis • Design for Analysis, Test, and Diagnostics • Device Analysis – Case Studies • Die Level Fault Isolation • Emerging FA Techniques and Concepts • FA at the Next Level – Boards and Systems • FA Process: Fault Isolation, Mechanisms, and Solutions • FIB Sample Preparation and Circuit Edit • Hardware Security and Counterfeiting • Keynote Presentations that open the conference with insights from global leaders in failure analysis, reliability engineering, and materials science. • Technical Sessions covering a broad range of failure analysis topics, including case studies, advanced characterization techniques, emerging technologies, and real-world industry applications. • Panel Discussions featuring experts from academia, industry, and government offering diverse perspectives on current challenges and future trends in the failure analysis community. • Microscopy Analysis and Materials Characterization • More than Moore: Integrating New Functions into Nanoelectronics • Nanoprobing and Electrical Characterization • Package Level Fault Isolation • Power Devices (Si, SiC, GaN) • Sample Preparation and Device Deprocessing • Scanning Probe Analysis • System-in-Package and 3D Devices • Workshops and Tutorials designed to provide handson learning and deeper engagement with advanced analytical methods and tools. • Exhibit Hall Hours where attendees can connect with leading suppliers, explore new instrumentation and technologies, and engage directly with solution providers. • Networking Opportunities, including the ISTFA Social Networking Event and additional communitybuilding activities throughout the week. • Student Competitions that support and celebrate the next generation of failure analysis professionals.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 4 EDFAAO (2026) 2:4-10 1537-0755/$19.00 ©ASM International® ELECTRICAL FAULT LOCALIZATION OF HIGH-DENSITY 3D INTERCONNECT VIA CHAINS THROUGH INNOVATIVE SAMPLE PREPARATION Kristof J.P. Jacobs imec, Leuven, Belgium kristof.j.p.jacobs@imec.be INTRODUCTION The growing demand for high-performance computing systems is driving innovation in system scaling. One emerging concept is CMOS 2.0, recently introduced by imec, where the system-on-chip (SOC) is divided into functional layers using system-technology co-optimization (STCO).[1] This concept is nowadays becoming practical thanks to recent breakthroughs in 3D interconnects and backside technologies. For example, wafer-to-wafer (W2W) hybrid bonding now enables sub-micron pitch interconnects, which are essential for stacking logic-on-logic or memory-on-logic. Backside power technology is also evolving toward enabling direct access to transistor terminals from the backside. At imec, dedicated test vehicles are used during development to validate advanced process technologies, with via chains playing a key role in yield analysis. While electrical testing of via chains can identify the presence of defects, failure analysis (FA) is required to localize the defective interconnect(s) and determine the root cause, enabling targeted process optimization. DEFECT LOCALIZATION IN VIA CHAINS USING OBIRCH AND LICA Optical beam-induced resistance change (OBIRCH) and light-induced capacitance alteration (LICA) are laser scanning based FA techniques that can be used for the localization of electrical open and short defects in via chains.[2,3] OBIRCH is effective for the localization of soft opens and leakage failures; however, it is not applicable for hard opens. In contrast, the LICA method, first proposed at ISTFA in 2016, is effective for the localization of hard open defects.[4] This is because the measurement principle of the LICA method relies on detecting laser-induced changes in the electrical capacitance, rather than laser-induced changes in the electrical resistance, being the case for the OBIRCH method. Figures 1a–c illustrate the application of OBIRCH to a wafer-to-wafer via chain containing a soft open defect, where the measured resistance of the chain exceeds its nominal value by approximately one megaohm. As shown in Fig. 1a, the resistance of the defective via chain is measured while the focused laser beam scans over the structure; when the beam hits a defective interconnect, the resulting local heating from the laser changes its electrical resistance, which generates a noticeable signal on the resistance meter. The change in the detected signal can be observed in the OBIRCH image (Fig. 1b) where the arrow points toward the location of the defective interconnect. The cross-sectional image in Fig. 1c shows an example of a high-resistance via, which has been localized using the OBIRCH technique. It should be noted that the OBIRCH image shown in Fig. 1b provides defect localization information only in the XY plane, which is generally adequate for relatively thin structures. However, it has also recently been shown that depth information can be extracted by analyzing the phase of the OBIRCH signal using a lock‑in detection approach.[5,6] This capability may be particularly useful for defect localization in more complex structures. Figures 1d–f illustrate the application of LICA to a W2W via chain containing a hard open defect. In this case, the measured chain resistance lies in the giga‑ to tera‑ohm range, resulting in negligible current flow through the measurement circuit, rendering OBIRCH ineffective. Figure 1d shows the principle of the LICA measurement. Unlike OBIRCH, the laser beam is not used to induce localized heating, but to generate electron-hole pairs in the underlying silicon substrate, thereby locally changing the electrical capacitance of the structure. To detect these capacitance changes, a capacitance meter is connected across the via chain and the substrate. Capacitance changes are detected only for interconnects that remain electrically connected to the capacitance meter. A hard
edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 open defect blocks signal propagation, leading to an observable change in contrast in the LICA image. In Fig. 1e, a pronounced contrast is visible within the dashed rectangle (i.e., the via chain region), transitioning from light red to dark red color, with the defect site marked by an arrow at the point of the observed contrast change. The cross-sectional image in Fig. 1f shows an example of an open via that has been localized using the LICA technique. Following the schematic diagrams shown in Figs. 1a and d, the silicon substrate of the top wafer is selectively removed above the via‑chain area prior to OBIRCH and LICA analysis. This enables the use of 405 nm laser excitation and already prepares the sample for subsequent physical analysis. Due to the shallow absorption depth of 405 nm light in silicon (less than 1 µm), the interaction volume is confined near the surface, which is advantageous for the LICA technique. In addition, shorter excitation wavelengths enable higher spatial resolution. Localized silicon removal has previously been demonstrated at the die level using wet etching and at the wafer level using dry etching.[7,8] EXTENSION ELECTRODES FOR HIGHRESOLUTION OBIRCH/LICA ANALYSIS The OBIRCH and LICA analyses in Fig. 1 were conducted at imec from the wafer frontside, where the probe pads are also located. Because electrical contact between the probe pads and the OBIRCH/LICA instruments is required during these analyses, either by direct metal probing or by wire bonding, it is critical that the objective of the laser scanning microscope (LSM) does not interfere with the probes or wire bonds, as depicted in Fig. 2a. An objective with a working distance (WD) of several millimeters is typically required for this purpose. While objectives with a lower numerical aperture (NA) meet this requirement, it is well known that the imaging resolution is also limited for such objectives. For example, an objective with an NA of 0.35 and a wavelength of 405 nm has a diffraction‑limited resolution of approximately 700 nm, according to Rayleigh’s criterion (0.61 λ/NA). It is evident that further improvements in imaging resolution are required to keep pace with the semiconductor scaling roadmaps. At the 2025 Symposium on VLSI Technology and Circuits, imec demonstrated the feasibility of extending the wafer‑to‑wafer hybrid bonding roadmap to a pitch of 250 nm.[9] Furthermore, imec’s nanoTSV roadmap now targets backside vias with diameters as small as 20 nm at a pitch of 120 nm. One well-established method to enhance imaging resolution is to use a backside solid immersion lens (SIL) in combination with an infrared laser. Using this approach, resolutions of 170 nm and 210 nm have been reported in the literature for GaAs SIL + 1064 nm and Si SIL + 1300 nm combinations, respectively.[10] Because the home‑built LSM‑based FA tool at imec does not presently support SIL integration, and the SIL method can (b) (a) (e) (c) (d) (f) Fig. 1 (a–c) Application of OBIRCH to a W2W via chain containing a soft open defect, and (d–f) LICA to a W2W via chain containing a hard open defect. The dotted rectangles in (b) and (e) outline the area where the via chain, which runs in a serpentinelike pattern, is located.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 6 be challenging to apply to small samples, an alternative solution was needed. While there is the possibility to further reduce the imaging wavelength from 405 nm into the ultraviolet, this approach is expected to introduce additional optical complexities that limit practical applicability. As a result, improving the NA of the imaging system is considered a more viable route to enhancing imaging resolution, although the associated working‑distance limitation must be addressed. One solution to this problem is illustrated in Fig. 2b. It involves fabricating extension electrodes directly on the chip during the sample-preparation stage, prior to electrical fault isolation. The purpose of these extension electrodes is straightforward: They route the probe pads from the active area toward the chip’s edge, thereby creating sufficient space for the objective lens to be positioned closer to the chip surface. This enables the use of a high‑NA objective with a much-reduced working distance, resulting in improved imaging resolution. Using this approach, theoretical imaging resolutions of 275 nm and 176 nm are predicted for air‑gapped and oil‑immersion objectives with NA values of 0.9 and 1.4, respectively. Figure 2c shows a section of a nanoTSV via chain imaged using an oil‑immersion objective with a NA of 1.4, in the configuration shown in Fig. 2b. The metal segments interconnecting the nanoTSVs measure 630 nm and 210 nm in the horizontal and vertical directions, respectively, at a vertical pitch of 420 nm. Among liquid‑immersion objectives, oil‑immersion objectives provide the higher NA value, typically up to approximately 1.4. For this application, oil is also preferred over water as the immersion medium due to its insulating property. However, achieving this level of imaging quality requires careful fabrication of the extension electrodes, as the oil‑immersion objective used in Fig. 2c has a working distance of only 100 µm. TECHNIQUES FOR THE FABRICATION OF EXTENSION ELECTRODES The fabrication of the extension electrodes must meet several key requirements: (1) the electrodes must be sufficiently thin to fit within the objective’s working distance; (2) they must remain electrically isolated from the surrounding chip circuitry to prevent short circuits; and (3) they should ideally exhibit low electrical resistance. The probe pads to which the electrodes must make contact are also typically small (e.g., 80 µm × 60 µm, with a pitch of 100 µm), which introduces additional challenges for the fabrication process. Two fabrication methods have been successfully developed over time to meet these requirements, in chronological order: (1) the stencil‑transfer method and (2) the metal inkjet printing method. STENCIL TRANSFER METHOD The stencil‑transfer method, schematically illustrated in Fig. 3a, involves sputtering a metal layer through a stencil with apertures that match the desired metallization pattern. The stencil is directly placed and aligned on the chip under test. Laser‑cut stainless‑steel stencils have proven to be a cost‑effective and accessible solution, owing to their widespread use as solder‑paste stencils in printed circuit board manufacturing. The metal deposition is performed using a table‑top sputter coater, commonly used for scanning electron microscopy sample preparation. Figure 3b shows an optical micrograph of Fig. 2 (a) OBIRCH imaging and probing performed from the same side of the chip require the use of a large‑working‑distance objective, at the expense of reduced NA. (b) Extending the contact pads from the region of interest to the edge of the chip using low‑profile electrodes enables the use of high‑NA air or liquid‑immersion objectives. (c) Optical microscope image of a nanoTSV via chain acquired using an oil‑immersion objective and a 405 nm imaging wavelength, following the configuration shown in (b). (a) (b) (c)
edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 the metallization structure after stencil removal, where two electrodes are deposited on the chip and contact a W2W via chain. In this case, a gold sputtering target was used. Additional details of the stencil‑transfer method are reported elsewhere.[11] While the stencil‑transfer method is attractive due to its simplicity and reliance on standard laboratory equipment, it has some limitations. A key limitation is the minimum achievable line width, which is typically on the order of 100 µm and largely depends on the laser‑cutting process used to fabricate the stencil. Furthermore, the method is challenged by samples that have significant surface topography, as the sputtering process is largely directional. Finally, the approach offers limited patterning flexibility, since each unique electrode layout requires a dedicated stencil. METAL INKJET PRINTING To overcome the limitations associated with the stencil‑transfer method, a metal inkjet printing approach was developed, as shown schematically in Fig. 3c.[12] This method enables the fabrication of conductive patterns using a drop‑on‑demand printing scheme, in which a conductive ink is precisely ejected from the printhead when actuated by a pulse signal applied to a piezoelectric transducer. A silver‑based ink was selected due to its high electrical conductivity, low tendency toward oxidation, and good chemical stability. The inkjet printing method offers high flexibility, enabling the rapid fabrication of customized electrodes and probe pads. The electrical resistance of the printed electrodes was measured to be approximately 8 Ω/mm, resulting in almost negligible impact on OBIRCH/LICA measurements. For applications requiring lower interconnect resistance and higher current‑carrying capacity, printing multiple lines in parallel and employing a multi‑pass printing strategy to increase the line width and thickness can be considered. Notably, the inkjet printing method enables the formation of significantly smaller features than the stencil‑ transfer approach, with minimum feature sizes below 70 µm. This capability can be further extended toward the micrometer-scale by using more advanced printing techniques, including aerosol printing. Figure 3d shows an optical micrograph of the metallization structure Fig. 3 (a) Stencil-based metal deposition method; (b) optical micrograph of the resulting metallization structure after stencil removal; (c) metal inkjet printing method; and (d) optical micrograph of the resulting metallization structure after inkjet printing. (a) (c) (b) (d)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 8 fabricated using the inkjet method, in which two silver electrodes are deposited on the chip and contact a via chain. For both deposition methods, an underlying dielectric layer is required to avoid electrical shorting between the fabricated electrodes and the chip under test. This dielectric layer is shown in blue in Figs. 3a and c and must also be patterned to open the region of interest and to create vias that allow the electrodes to contact the probe pads (sized at 80 µm × 60 µm). FABRICATION OF THE DIELECTRIC LAYER To minimize the fabrication complexity of the dielectric layer and ensure compatibility with a FA laboratory environment, a polyimide material was selected, as it can be readily deposited and patterned without the need for advanced processing equipment. The process flow is illustrated in Fig. 4. A thin photo-patternable polyimide layer is first spray‑coated onto the test chip from an aerosol can, resulting in a film thickness between 1.5 and 2.0 µm (Fig. 4a). The layer is subsequently exposed (Fig. 4b) to define openings in the region of interest and to form vias. Maskless lithography can be readily implemented using direct laser exposure at a wavelength of 405 nm, either with a defocused laser beam or, as recently demonstrated at ISTFA 2024, using a modified office projector.[13] After exposure, the sample undergoes development in an aqueous sodium hydroxide solution (Fig. 4c), followed by a curing step on a hot plate at 240°C for 10 min to ensure complete removal of the carrier solvent and to enhance the chemical, electrical, structural, and thermal stability of the polyimide layer. In addition, the curing process induces partial reflow of the polyimide, resulting in smoother via sidewalls (Fig. 4d), which improves layer conformality during subsequent metal deposition. Based on the intended metallization approach, either stencil‑based deposition or inkjet printing is then selected for metal deposition. The total structure thickness (dielectric and conductive layers) measures less than 3 µm and the complete fabrication flow shown in Fig. 4 can be completed within 2 hours. FAILURE ANALYSIS OF A nanoTSV CHAIN Figure 5 shows a photograph of the test chip prepared using the inkjet‑printing sample‑preparation process for the localization of leakage failures in a nanoTSV chain (Fig. 2c) within a backside power‑delivery‑network test vehicle. Electrical contact to the inkjet‑printed probe pads is achieved using low‑profile spring pins. The probe pads (a) (b) (c) (d) (e) (f) Fig. 4 Step‑by‑step fabrication process flow illustrating the creating of the patterned dielectric layer (a, b, c, d) and the on‑chip extension electrodes (e, f).
edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 have dimensions of 1.2 mm × 1.2 mm, and the applied spring‑pin force ensures reliable positioning of the sample on the printed circuit board (PCB) carrier without the use of adhesive, allowing for straightforward mounting and removal. The right panel of Fig. 5 shows an optical image of the region of interest, illustrating the connection between the electrodes and the probe pads. Each electrode has a length of 8 mm, corresponding to an estimated total parasitic resistance of approximately 128 Ω for two electrodes in the measurement circuit. High‑resolution OBIRCH analysis was performed using the oil‑immersion measurement configuration shown in Fig. 2b. Figure 6a shows a pattern image of the scanned nanoTSV chain, while Fig. 6b presents the measured OBIRCH signal. The high imaging resolution enabled accurate localization of the defect. A transmission electron microscopy (TEM) image of a localized defect using this method is shown in Fig. 6c. The root cause of the observed leakage failures was identified as partial filling of the nanoTSVs, leading to a lowering of the backside metal layer and resulting in a direct short to the substrate. CONCLUSION A novel approach is introduced that expands the applicability of optical‑microscopy‑based FA techniques, including LICA and OBIRCH, to increasingly downscaled device structures. It overcomes the working‑distance limitations of high‑NA objectives when probing and imaging must be performed from the same side of the chip. Two fabrication methods—stencil‑based metal transfer and metal inkjet printing—were developed to realize on‑chip extension electrodes. While the stencil‑based approach offers simplicity and rapid implementation, the inkjet‑printing method enables finer feature sizes and increased layout flexibility. The methodology was successfully demonstrated through the localization of a leakage failure in a fine‑pitch nanoTSV chain. (a) (b) (c) Fig. 5 Left, photograph of the test chip with inkjet‑printed electrodes mounted on a PCB carrier. Electrical contact to the inkjet‑printed probe pads is achieved using spring pins. Right, optical micrograph illustrating the connection between the electrodes and the probe pads. Fig. 6 Application of high‑resolution OBIRCH to a leaky nanoTSV chain: (a) pattern image (field of view: 10 µm × 10 µm); (b) corresponding OBIRCH image; and (c) TEM cross‑section at a defective area identified by OBIRCH.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 10 REFERENCES 1. Z. Tokei, et al.: “A Path to High-density Front and Backside Wafer Connectivity,” Chip Scale Review, 29(4), p. 20-29, Jul.-Aug. 2025. 2. K. Nikawa and S. Inoue: “New Capabilities of OBIRCH Method for Fault Localization and Defect Detection,” Proceedings Sixth Asian Test Symposium (ATS ’97), Akita, Japan, 1997, p. 214-219, doi.org/10.1109/ ATS.1997.643961. 3. K.J.P. Jacobs, et al.: “Fault Isolation of Resistive/Open 3-D Wafer Bonding Interconnects by Thermal Laser Stimulation and LightInduced Capacitance Alteration,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), Nov. 2020, p. 6-11, doi.org/10.31399/asm.cp.istfa2020p0006. 4. K.J.P. Jacobs, et al.: “Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3-D Integration,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2016, p. 418-425, doi.org/10.31399/ asm.cp.istfa2016p0406. 5. K.J.P. Jacobs, et al.: “Lock-in Thermal Laser Stimulation for Nondestructive Failure Localization in 3D Devices,” Microelectronics Reliability, 2017, 76-77, p. 188-193, doi.org/10.1016/j.microrel. 2017.06.034. 6. H. Kim, et al.: “3D-VNAND Depth Measurement using OFI Lock-In OBIRCH,” Proc. Int. Symp. Test. Fail. Anal., 2025, p. 563-566, doi. org/10.31399/asm.cp.istfa2025p0563. 7. K.J.P. Jacobs and E. Beyne: “Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects,” IEEE Transactions on Semiconductor Manufacturing, Nov. 2023, 36(4), p. 673-675, doi. org/10.1109/TSM.2023.3311452. 8. K.J.P. Jacobs, M. Stucchi, and E. Beyne: “Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy,” IEEE Transactions on Instrumentation and Measurement, 2021, 70, p. 1-7, Art no. 3523907, doi.org/10.1109/ TIM.2021.3108531. 9. L. Witters, et al.: “High-Density Wafer Level Connectivity using Frontside Hybrid Bonding at 250 nm Pitch and Backside Through- Dielectric Vias at 120 nm Pitch After Extreme Wafer Thinning,” 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025, p. 1-3, doi.org/10.23919/VLSITechnologyandCir65189. 2025.11075104. 10. X. Mao, et al.: “High Resolution Imaging of Thick SI Device using Doublet SIL,” Proc. IEEE Int. Symp. Phys. Fail. Anal. Integr. Circuits (IPFA), 2020, p. 1-5, doi.org/10.1109/IPFA49335.2020.9260936. 11. K.J.P. Jacobs: “Enhancing Imaging Resolution of Microscopy-based Debug Techniques with On-chip Microelectrodes,” 43rd NANO Test. Symp. (NANOTS), Nov. 2023, p. 125-130. 12. K.J.P. Jacobs: “Inkjet-printed Electrical Interconnects for High Resolution Integrated Circuit Diagnostics,” Commun Eng 2, 2023, 21, doi.org/10.1038/s44172-023-00073-4. 13. K.J.P. Jacobs, et al.: “Innovations in Beam-based Defect Localization Methods for Advanced 3D Interconnects,” Proc. Int. Symp. Test. Fail. Anal., 2024, p. 231-241, doi.org/10.31399/asm.cp.istfa2024p0231. ABOUT THE AUTHOR Kristof J.P. Jacobs is a principal member of technical staff in the Advanced Reliability Robustness and Test (AR2T) department at imec in Leuven, Belgium. He obtained his Ph.D. in electrical and electronic engineering in 2015 from the University of Sheffield, U.K. His doctoral work contributed to the development of resonant tunneling diodes for terahertz sensing and communication applications. He joined imec in 2015 where his research focuses on advancing failure analysis methods for advanced compute and memory technologies. IPFA 2026 The 33rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) will be held July 13-16 at the Marina Bay Sands in Singapore. The event will focus on cutting-edge research in failure analysis, reliability, and specialized technology within integrated circuits. Topics include advanced fault isolation techniques, physical and package-level failure analysis, transistor reliability, ESD and latch-up mechanisms, and the integration of AI for failure detection and reliability assessments. The symposium is technically sponsored by the IEEE Electron Devices Society. For more information, visit the IPFA website at ipfaieee.org/2026. NOTEWORTHY NEWS
edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 NOTEWORTHY NEWS MICROSCOPY & MICROANALYSIS MEETING 2026 The Microscopy & Microanalysis (M&M) 2026 meeting will be held August 2-6 in Milwaukee. The scientific program features the latest advances in biological, physical, and analytical sciences as well as techniques and instrumentation. Complementing the program is one of the largest exhibitions of microscopy and microanalysis instrumentation and resources in the world. Educational opportunities include a variety of Sunday short courses, tutorials, workshops, and pre-meeting congresses for early-career scientists. M&M is sponsored by the Microscopy Society of America, the Microanalysis Society, and the Microscopical Society of Canada. For more information, visit mmconference.microscopy.org. CAM-WORKSHOP 2026 The 13th CAM-Workshop on Failure Analysis and Material Diagnostics for Electronic Components will take place on May 19-20 in Halle, Germany. The CAM-Workshop brings together experts from the electronics industry and materials diagnostics equipment manufacturers. The goal of the event is to discuss challenges and future requirements in the field of failure analysis and materials characterization of electronic devices, sensors, and systems. The event includes oral presentations as well as an industrial exhibition. For more information, visit cam-workshop.de.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 12 INSPECTION AND METROLOGY CHALLENGES IN HYBRID BONDING Himanandhan Reddy Kottur, Pavanbabu Arjunamahanthi, Liton Kumar Biswas, Istiaq Firoz Shiam, Katayoon Yahyaei, and Navid Asadizanjani Department of Electrical and Computer Engineering, University of Florida, Gainesville h.kottur@ufl.edu EDFAAO (2026) 2:12-24 1537-0755/$19.00 ©ASM International® INTRODUCTION The semiconductor industry is experiencing a paradigm shift from traditional monolithic system-on-chip (SOC) architectures toward heterogeneous integration (HI) based on chiplet design.[1,2] This evolution stems from the growing demand for higher performance, energy efficiency, and design flexibility as transistor scaling reaches physical and economic limits. Instead of a single large die, complex systems are now partitioned into multiple smaller chiplets, each optimized for specific functions such as logic processing, memory, or I/O operations. Subsequently, these chips are interconnected within a single package, achieving system-level performance comparable to that of monolithic SOCs while improving manufacturing yield, scalability, and cost efficiency.[3] At the heart of this transformation lies hybrid bonding, a key enabler for fine-pitch, high-density interconnects essential for 3D integration and chipletbased architectures.[4] Unlike conventional solder-based interconnects, hybrid bonding establishes direct copperto-copper (Cu-Cu) and dielectric-to-dielectric contacts, eliminating the need for solder bumps and underfill.[5] This advancement reduces parasitic resistance and capacitance, leading to enhanced electrical performance and lower power consumption. The technology has rapidly become foundational for stacking logic-memory modules, integrating high-bandwidth memory (HBM), and assembling artificial intelligence (AI) accelerators that demand compact form factors and superior signal.[6,7] The various applications of hybrid bonding are illustrated in Fig. 1. Additionally, hybrid bonding offers superior thermal conductivity and mechanical stability, critical for mitigating the heat and stress challenges inherent in dense 3D systems.[8] However, the inspection and metrology of hybrid bonding remain among the most critical challenges to ensuring bonding quality, process control, and long-term reliability. The bonding process demands nanometerscale planarity and cleanliness, where even minor surface roughness, contamination, or misalignment can degrade bond integrity. As bonding pitches continue to scale down, the difficulty of detecting and characterizing such defects increases dramatically. Traditional inspection techniques often lack the spatial resolution or sensitivity required to identify interfacial anomalies such as voids, delamination, or incomplete copper contact, especially when these features are buried beneath dielectric layers. Moreover, conventional metrology methods struggle to differentiate between mild topographical variations and defects Fig. 1 Hybrid bonding interconnects in various electronic technologies.
edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 capable of inducing reliability failures such as copper diffusion, dielectric separation, or interfacial cracking. The objective of this study is to identify and analyze the inspection and metrology challenges inherent to hybrid bonding across all process stages. The discussion focuses on defect sources related to planarization, alignment, and thermal bonding, and evaluates the performance limits of current nondestructive inspection technologies. In addition, this article explores emerging AI-assisted frameworks that integrate multiple imaging modalities to improve defect coverage and process insight. Through this analysis, the work aims to outline existing bottlenecks and propose a pathway toward scalable and adaptive inspection methodologies suitable for next-generation chiplet-based integration. OVERVIEW OF THE HYBRID BONDING PROCESS Hybrid bonding represents a sophisticated interconnect technology that enables the direct joining of two surfaces, each patterned with copper pads embedded within dielectric layers, through the synergistic application of mechanical, chemical, and thermal processes. In contrast to conventional solder bump-based methods, hybrid bonding eliminates solder connections, which allows significantly higher interconnect densities, a critical requirement for contemporary 3D integration and chiplet-based architectures. By simultaneously combining dielectric-to-dielectric and metal-to-metal bonding mechanisms within a single interface, the process establishes a mechanically robust and electrically stable connection between stacked components that supports structural integrity. An illustration of an advanced package structure with hybrid bonding interconnects and their key manufacturing-induced defect locations is shown in Fig. 2. The wafer-to-wafer (W2W) and chip/die-to-wafer (C2W/D2W) hybrid bonding process can be systematically partitioned into four fundamental stages: surface planarization, surface activation, precision alignment, and thermal bonding. Each stage exerts a pivotal influence on the overall reliability and functional performance of the bonded interface. Surface planarization establishes a high degree of topographical uniformity, enabling intimate contact between opposing wafers or Fig. 2 (a) Advanced package interconnected with hybrid bonding technology. (b) Critical hybrid bonding manufacturing-induced defects highlighted in an advanced package. (a) (b)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 14 dies.[9] Surface activation alters the chemical state of the copper and dielectric surfaces to promote adhesion and facilitate atomic diffusion. Precision alignment ensures that bonding pads are positioned with nanometer-level accuracy, mitigating the risk of misalignment-induced defects.[10] Finally, thermal bonding consolidates the interface by promoting copper diffusion and generating a continuous metallurgical connection, which is critical for sustaining long-term electrical and mechanical stability. The ultimate performance and reliability of hybrid bonds are strongly contingent upon the precision and uniformity attained across each of these stages. Minor deviations in surface planarity, chemical activation, or alignment can induce the formation of voids, delamination, or increased interconnect resistance, thereby compromising functional integrity. In the wafer-to-wafer hybrid bonding process flow, defects originating at each stage due to manufacturing conditions and process variations are shown in Fig. 3. Accordingly, rigorous inspection and metrology are integral to the bonding workflow, providing continuous feedback and statistical process control to ensure consistent interface quality and reproducibility across wafers and high-volume production lots. SURFACE PLANARIZATION Surface planarization constitutes a fundamental prerequisite for achieving robust and reliable hybrid bonding, as it ensures that both bonding surfaces, typically comprising copper pads embedded within silicon dioxide or low-k dielectric matrices, exhibit nanometer-scale flatness and coplanarity. Achieving such stringent uniformity relies on chemical mechanical planarization (CMP), a process that integrates mechanical abrasion with chemical etching to systematically remove surface irregularities and produce a consistently smooth topography across the wafer. In the context of hybrid bonding, maintaining planarity within a few nanometers across the active bonding area is essential to prevent incomplete copper-to-copper contact. Even minimal height variations resulting from CMP-induced dishing, erosion, or residual pattern topography can generate localized voids or air gaps, leading to partial bonding, electrical discontinuities, or eventual delamination during subsequent thermal cycling. Surface roughness at the nanometer scale further influences the initial dielectric-to-dielectric adhesion phase, where van der Waals forces dominate; a smoother surface promotes more uniform atomic contact and facilitates consistent copper diffusion during the annealing step, thereby enhancing interfacial integrity. SURFACE ACTIVATION Following planarization, both bonding surfaces undergo a surface activation step designed to remove residual contaminants, native oxides, and organic residues that may have accumulated on the exposed copper pads.[12] Copper surfaces are inherently prone to oxidation under ambient conditions, forming a thin insulating layer that impedes atomic diffusion and undermines the formation of metallic bonds. The objective of surface activation is therefore to restore the copper and dielectric surfaces Fig. 3 Hybrid bonding wafer-wafer process flow and the defects originated at each stage.[11]
edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 to a chemically active state conducive to direct bonding, thereby enhancing adhesion and facilitating reliable metallurgical connections.[13] Surface activation is typically achieved through a combination of plasma treatments and wet chemical processes. Plasma-based methods, employing gases such as argon, hydrogen, or forming gas, effectively remove surface oxides and simultaneously increase surface energy, rendering the dielectric layers more hydrophilic and promoting uniform dielectric-to-dielectric contact. Wet chemical treatments, including formic acid or citric acid solutions, selectively dissolve copper oxides while minimizing surface roughening, thereby preserving planarization integrity. In advanced process flows, activa- tion may be performed in situ within the bonding chamber to prevent re-oxidation prior to wafer contact, ensuring that the surfaces retain maximal reactivity at the moment of bonding. The efficacy of surface activation is typically evaluated through a combination of indirect and direct metrology techniques. Contact angle measurements and surface energy analyses provide rapid assessment of wettability and chemical reactivity, while x-ray photoelectron spectroscopy (XPS) or auger electron spectroscopy (AES) offer quantitative characterization of residual oxide thickness and elemental composition.[14] Effective activation not only enhances bond yield but also permits bonding at reduced temperatures, mitigating thermal stress and improving compatibility with heterogeneous materials and complex device architectures. In high-volume manufacturing, continuous monitoring and feedback control of activation parameters are critical to ensure process uniformity, minimize defect formation, and maintain consistent interfacial quality across all wafers and dies. ALIGNMENT Precision alignment constitutes a pivotal stage in hybrid bonding, directly determining the spatial registration of copper pads and dielectric features on opposing wafers or dies. Given the sub-micrometer interconnect pitches characteristic of modern chiplet-based architectures, alignment tolerances often demand positioning accuracy within ±100 nanometers or less. Achieving such tolerance necessitates the integration of high-resolution imaging, advanced metrology, and motion control systems capable of compensating for both global and local variations in wafer geometry. Alignment is conventionally performed using optical or near-infrared (IR) imaging systems that detect fiducial markers patterned on each bonding surface. For silicon-based substrates, which are opaque to visible light beyond a few micrometers of thickness, IR illumination is employed to penetrate the wafer and locate buried alignment features. The imaging data are processed to determine translational, rotational, and vertical offsets, which are subsequently corrected through precision motion stages with nanometer-scale resolution. Maintaining this level of precision is complicated by factors such as thermal expansion, mechanical vibrations, and environmental drift, all of which can induce systematic misalignment across the bonding interface. To mitigate these effects, bonding equipment is typically operated within temperature-controlled, vibration-isolated environments, and in some systems, active feedback loops are employed to continuously adjust wafer positioning in real time. In die-to-wafer bonding configurations, where individual dies are sequentially placed onto a target wafer, adaptive alignment algorithms are particularly critical for ensuring consistent overlay accuracy across the entire substrate. Misalignments in lateral, rotational, or vertical axes, even on the order of tens of nanometers, can compromise pad-to-pad contact, resulting in open circuits, shorting, or increased interconnect resistance. Post-alignment verification is therefore conducted using high-resolution optical microscopy, infrared imaging, or scatterometry to confirm fiducial registration, detect die tilt or wafer warpage, and validate uniform contact prior to thermal bonding. The integration of these alignment and metrology practices establishes a robust foundation for achieving high yield, reliable interconnect formation, and reproducible electrical performance across hybridbonded assemblies. THERMAL BONDING Thermal bonding represents the culminating stage of the hybrid bonding process, wherein both mechanical and chemical adhesion are established across the interface to form a robust metallurgical connection. Following sur- face planarization, activation, and alignment, the wafers or dies are brought into contact under controlled pressure, initiating dielectric-to-dielectric adhesion dominated by van der Waals and hydrogen bonding interactions. This preliminary contact ensures intimate engagement of the surfaces, facilitating subsequent copper-to-copper atomic diffusion during thermal annealing. Annealing temperatures typically range from 200 to 400°C, depending on material composition, bonding pitch, and process specifications.[15] During thermal bonding, copper atoms migrate across the interface to establish continuous metallic inter-
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