DESIGN FOR DEBUG: INTEGRATING FA INTO FUTURE TECHNOLOGIES Abstract submission deadline: April 3, 2026 CALL FOR PAPERS NOW OPEN! OCTOBER 4–8, 2026 HENRY B. GONZALEZ CONVENTION CENTER, SAN ANTONIO, TEXAS Traditionally, failure analysis has often been treated as an afterthought in chip design. However, as architectures grow more complex and increasingly difficult to debug, it’s essential to integrate diagnostic capabilities from the outset. Let’s define proactive strategies that position us for success when qualifying the most advanced packages and emerging technologies. Come to share your experiences and advance the industry and your career at the International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community. We invite you to submit your work for publication and to present it to the community in San Antonio, Texas, for the 52nd year of ISTFA. • Standardize debug protocols for GAA, chiplets, stacked die, backside power, high-speed I/Os, and emerging silicon photonics • Leverage AI for smarter fault isolation, and to enable faster/better fault diagnosis results • Collaborate across teams—FA, design, test, and tool vendors—to tackle emerging tech challenges using unified, rather than independent, approaches • Emerging FA Techniques and Concepts • Die Level Fault Isolation • Package Level Fault Isolation • System-in-Package and 3D Devices • Wide Bandgap Power Devices (SiC, GaN, new materials) • AI Applications for Failure Analysis • Boards and Systems • Sample Preparation and Device Deprocessing • Discuss embedding FA-specific features like CAD alignment cells, routing internal nodes for e-beam and active-nanoprobe accessibility, and adding on die sensors for real-time monitoring of power and speed path measurement • Utilize big data and dynamic testing to pinpoint yield issues earlier in technology introduction phase • Original, unpublished, and novel material is being solicited on testing, analysis, characterization, and metrology of electronic devices and systems from the nanoscale and upward. • Case studies, review papers, and non-commercial work from vendors are encouraged. Paper selection is based entirely on information submitted in abstracts and will be evaluated on novelty, completeness, quality, and benefit to the FA community. Abstracts should be a minimum of two pages long, including images and figures. References are required. Original, unpublished abstracts are solicited in the following topic areas: • FIB Sample Preparation and Circuit Edit • Microscopy Analysis and Materials Characterization • Case Studies: Device Analysis • Case Studies: FA Process and Workflows • Product Yield, Test, and Diagnostics • Silicon Photonics and Co-Packaged Optics • Trusted Electronics
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