edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 1 32 suggesting a broad spectrum of readiness across organizations. The same holds for failure-mode categorization: Some teams use databases or spreadsheets, while others reported no structured storage at all, underscoring the need for harmonized taxonomies and scalable infrastructure. When asked where AI could help most, attendees emphasized interpretation and improvement of analysis results, along with assistance and automation for tool operation. Notably, participants showed tolerance for ISTFA 2025 SAMPLE PREP USER GROUP Chair/Co-Chairs: Jim Colvin, Pawel Nowakowski, Bryan Tracy, and Nathan Bakken jim@fainstruments.com, p_nowakowski@fischione.com, bryan.tracy@ibssgroup.com, nathan.j.bakken@intel.com Sample Prep User Group presenters and co-chairs. occasional AI agent errors, with very few rejecting such tools outright. In conclusion, the group endorsed a cautious but constructive path: start with public data and proofs of concept, keep experts in the loop, clarify legal and governance frameworks (with NDAs covering sensitive elements), and explore academic and synthetic data avenues to demonstrate value without compromising confidentiality. The ISTFA 2025 Sample Prep User Group session, sponsored by Ultra Tec, gathered over 80 attendees for a critical discussion on the latest challenges in preparing advanced devices and advanced package samples for failure analysis. The session was led by panelists Jon Scholl from Battelle and Susan Li from Marvell Technology. Scholl initiated the discussion by focusing on IC delayering for shrinking feature sizes. Technical optimization was a key theme, specifically maximizing optical microscopy using tools with oil immersion lenses. The panel endorsed combining dry etch and mechanical polishing for achieving sample flatness, while raising concerns over the inconsistent and potentially damaging nature of laser delayering. A vigorous debate centered on maintaining planarity when preparing thin functional layers, stressing the necessity of iterative inspection and using sacrificial materials for protection. This was followed by Susan Li addressing the unique difficulties of 2.5D and 3D advanced packaging, citing challenges with large device preparation and relieving the mechanical stress introduced by polishing, which complicates fault isolation. Li also highlighted the perception that FA is often an afterthought in the design process. This led to a critical discussion on advocating for design-for-test (DFT) standards and implementing pre-emptive measures such as built-in self-test. Attendees supported this, confirming their commitment to robust DFT. The open mic segment covered various primer topics highlighted by the following: • Strain Management: Techniques to mitigate stress artifacts were discussed, including the counterintuitive method of creating minor delaminations to allow the target zone to relax. • AI in Sample Preparation: The potential of AI was explored. While currently expensive, the consensus was that its most practical application is in high-volume manufacturing yield enhancement, primarily for vision-based layer recognition, rather than unique, low-volume FA. • Justifying Lab Tools: Panelists stressed demonstrating the value of expensive equipment to management by explaining the complexity of modern analysis and showcasing the significant cost payoff. They emphasized that equipment costs are minimal compared to the cost of production downtime caused by unresolved failures. The successful discussion concluded, generating anticipation for the next ISTFA in San Antonio.
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