edfas.org 29 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 1 expertise. It is no longer feasible for a single individual to execute the entire workflow; instead, the process demands real-time collaboration among domain experts specializing in specific techniques. Defining the “Chiplet.” To ensure clarity amidst industry buzzwords, the panel solidified the definition of chiplets. It was defined not just as a hardware component, but as a design method characterized by two pillars: 1) Disaggregation: breaking a monolithic SoC into optimized functional components (I/O, memory, cores) and 2) Advanced packaging: re-integrating these components with high-bandwidth connections that mimic the performance of a single chip. Emerging Techniques (3D Magnetic Inverse). The discussion highlighted the 3D magnetic inverse technique as a high-potential solution for the future. Although currently in the theoretical and simulation stage, this technique has demonstrated the capability to localize faults with sub-micron precision in three dimensions. Once mature, the industry vision is to combine this magnetic inverse capability with 3D x-ray tomography in a single machine. This multimodal approach would allow for nondestructive, high-precision fault localization, potentially solving the “blindness” issues caused by complex 3D stacks. CONCLUSION The panel reached a consensus that business as usual in failure analysis is over. The complexity of heterogeneous packaging demands a three-pronged evolution: the adoption of AI to interpret complex data, the development of new physics-based tools (like 3D magnetic inverse), and a cultural shift toward collaborative, cross-functional teams replacing the “lone wolf” analyst. ISTFA 2025 USER GROUP HIGHLIGHTS Anita Madan,* Cecile S. Bonifacio,** and Jayant D’Souza*** ISTFA 2025 User Group Chair/Co-Chairs *Independent Consultant, New York, N.Y. — amadan16@gmail.com **E.A. Fischione Instruments, Export, Pa. — cs_bonifacio@fischione.com ***Siemens EDA, Wilsonville, Ore. — jayant.dsouza@siemens.com The 51st ISTFA conference, held in Pasadena, Calif., from November 16 to 20, 2025, featured six dynamic, in-person User Group sessions designed for industry professionals and researchers to share insights, innovations, and methodologies in the field. These sessions served as a vital forum alongside the technical program, emphasizing active engagement, networking, and ongoing dialogue on critical industry topics. The goal was to foster discussions that extended beyond the formal conference setting. The structure varied; some sessions utilized leading expert panelists to initiate discussions on relevant FA topics, such as the goals of the FA Technology Roadmap. Live polls were used to gauge and incorporate audience interests, experiences, and immediate problem-solving issues. Some sessions focused entirely on exploring specific failure analysis methodology for current industry challenges and best practices. Drawing insights from a broad cross-section of professionals—including analysts from leading semiconductor companies, tool vendors, and academic representatives— participation was highly enthusiastic across all six groups. The sessions maintained their reputation, receiving positive feedback from attendees for their valuable content, interactive format, and exceptional engagement. Participants were encouraged to continue their collaborative exchange of ideas via ASM Connect’s community boards. A presentation during the AI User Group session.
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