edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 1 28 A SUMMARY OF THE ISTFA 2025 PANEL DISCUSSION: SCALING BEYOND MOORE’S LAW: HETEROGENEOUS COMPUTING AND ADVANCED PACKAGING Wentao Qin* and Greg Johnson** ISTFA 2025 Panel Discussion Organizers *Microchip Technologies Inc., Chandler, Ariz. — wentao.qin@microchip.com **Carl Zeiss Microscopy, White Plains, N.Y. — greg.johnson@zeiss.com The 2025 Panel Discussion, held November 19, was convened to address the industry’s pivot from monolithic system-on-chip (SoC) designs to heterogeneous integration. While this shift enables continued performance scaling, it has precipitated a crisis in reliability and failure analysis (FA). The session highlighted that the accelerating cadence of new package architectures is outpacing current FA capabilities, necessitating a fundamental transformation in workflows, tools, and cross-domain collaboration. Panelists included: Bernice Zee, AMD, Navid Asadi, University of Florida, Susan Li, Marvell Technology, and Boris Vaisband, University of California, Irvine. Bernice Zee opened the session by defining the “cadence crisis.” With new architectures emerging almost annually, the boundaries between silicon and package FA are dissolving. The presentation posited a provocative question: Are we facing the end of the era of nondestructive testing? As packages become denser, destructive sample preparation is becoming a prerequisite for imaging, fundamentally changing the FA triage process. The discussion moved to the “trenches” of current lab challenges. Susan Li noted that technologies such as backside power delivery are rendering traditional optical probing tools (like laser voltage imaging) ineffective by blocking access to transistors. Simultaneously, the integration of co-packaged optics introduces photonics-based failure modes that electrical engineers are ill-equipped to analyze, creating a massive skills and equipment gap. Addressing these gaps, the panel and Navid Asadi explored artificial intelligence. AI was presented as the key to “bearing the brunt” of data fragmentation. By creating AI-powered digital twins, labs can fuse low-resolution or noisy data from disparate tools (SEM, SAM, x-ray) to reconstruct failure sites that no single tool can resolve on its own. Boris Vaisband concluded the session with a visionary look at the system-on-wafer. This concept eliminates the organic package entirely, placing chiplets on an active silicon interconnect fabric. While solving electrical scaling issues, this architecture introduces new challenges, such as the impossibility of traditional rework, driving the need for intelligent fabrics capable of self-test and self-repair. OPEN DISCUSSION The Q&A session focused on defining the new terminology of the era and addressing the operational shifts required to manage it. Redefining the FA Workflow. A major topic of discussion was the blurring boundary between package fault isolation and physical analysis. Historically, these were linear, distinct steps handled by separate individuals. The panel concluded that in the era of heterogeneous integration, this linear workflow is obsolete. Fault isolation now requires deep, iterative support from physical analysis and sample preparation. The panel concluded that optimizing the workflow requires a “heterogeneous integration” of human “WITH NEW ARCHITECTURES EMERGING ALMOST ANNUALLY, THE BOUNDARIES BETWEEN SILICON AND PACKAGE FA ARE DISSOLVING.”
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