edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 1 20 switches to the 35% area ROI mask to acquire frames for weak site(s). Figure 8 depicts the correlation between the number of captured frames and normalized acquisition time. Assuming that 10 frames sufficiently identify both strong and weak sites, the traditional approach would necessitate a total of 10 units of time. In contrast, the double ROI mask approach allows the acquisition of 35 frames for strong sites and 15 frames for weak sites, resulting in a substantial enhancement in acquisition efficiency and overall site identification, as illustrated by the purple line in the graph. CONCLUSION This work demonstrates that SAILS significantly reduces laser-scanning analysis time by dynamically modulating dwell time through an external microcontroller and LabVIEW implementation, enabling a fully toolagnostic solution. Beyond SDL, the technique is readily adaptable to other laser-based FI methods such as TIVA, OBIRCH, and LADA. The array-based reconstruction and site-detection methodology further improve data fidelity, site coverage, and weak-site detection compared to traditional cumulative averaging. Simulated and experimental studies confirm enhanced accuracy and efficiency across varying site intensities and area constraints. Overall, the proposed workflow enables true automated SDL capable of prioritizing both weak and strong sites, offering a more robust and efficient foundation for future advancements in fault-isolation imaging analysis. ACKNOWLEDGMENTS All rights reserved. AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. REFERENCES 1. Y. Seah, M. Palaniappan, and J.M. Chin: “Applications of Soft Defect Localization (SDL) on AMD Advanced SOI Microprocessors,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2006. 2. D. Bodoh and K. Erington: “LADA and SDL: Powerful Techniques for Marginal Failures,” Microelectronics Failure Analysis Desk Reference, 2019, p. 410-414. 3. A.K. Karunanithi, et al.: “LADA Synchronization for Symmetric and Asymmetric ATE Test Program Cycles,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2019. 4. D. Bodoh and K. Erington: “Improving the DLS Workflow,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2012. ABOUT THE AUTHORS Arun Karunanithi is the device analysis lab manager at AMD Austin, bringing over 10 years of FI/FA experience since beginning as a co‑op working on 28 nm technologies. He holds an M.S. in mechanical engineering from the University of Texas at Dallas and specializes in advanced fault‑isolation techniques including LIT, IR thermal mapping, LVx, SDL, and a range of photon‑ and laser‑based methodologies. Since 2025, Karunanithi has served as the vice-president of EDFAS Lonestar Chapter. Benny Hsu is a senior device analysis engineer with a diverse background. He holds an M.S. in electrical and computer engineering from the University of Florida and an M.S. in applied mechanics from National Taiwan University. Kent Erington holds both a BSEE and MSEE from the University of Nebraska. With extensive experience in semiconductor failure and debug analysis, Erington has contributed to Motorola, Cirrus Logic, Freescale, NXP, and now at AMD as a primary member of the technical staff. Kent has authored multiple papers and holds several patents in the field of laser-based fault isolation. Joe Caroselli has over 15 years of experience in semiconductor failure analysis, specializing in fault isolation techniques. He managed the Failure Analysis Lab at AMD in Austin for six years before transitioning to the volume diagnostics team, where he focuses on data analytics for wafer sort diagnostics. Since 2020, Caroselli has served as chair of the EDFAS Lonestar Chapter, fostering collaboration and knowledge-sharing within the failure analysis community.
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