edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 48 also increases. Deca Technologies and Silicon Storage Technology (SST) have entered into a strategic agreement to develop a comprehensive non-volatile memory (NVM) chiplet package to facilitate customer adoption of modular, multi-die systems. PRODUCT NEWS Ted Kolasa, Northrop Grumman ted.kolasa@gmail.com PRESS RELEASE SUBMISSIONS: MAGAZINES@ASMINTERNATIONAL.ORG BOOSTER ETCH AUTOMATED LAB Working with customer feedback, JIACO Instruments has developed the latest innovation for microwave induced plasma (MIP) machines: the Booster Etch Automated Lab. JIACO Instruments is well known for developing MIP and providing MIP decapsulation systems for failure analysis and reliability labs. MIP decapsulation is a technique used to remove the encapsulating material from integrated circuit (IC) packages, allowing for failure analysis and access to the underlying chip and wire bonds. It utilizes atmospheric pressure plasma with oxygen and patented hydrogen-based recipes, offering advantages over conventional plasma etching methods. Booster Etch is a new option for JIACO’s MIP machines, increasing the sample processing speed by up to 100%. Other advantages of Booster Etch include retention or the high-etch selectivity inherent in MIP decapsulation and reduction in operating costs. Booster Etch is a paid upgrade available to all customers. The hardware and software requirements will vary per customer. For more information, visit jiaco-instruments.com. COLLABORATION TO ENABLE NON-VOLATILE MEMORY CHIPLET SOLUTIONS As traditional monolithic chip designs grow in complexity and increase in cost, the interest and adoption of chiplet technology in the semiconductor industry Booster Etch Automated Lab increases sample processing speed up to 100%. The collaborative solution provides a modular, memory-centric foundation for advanced multi-die architectures by combining the strengths of both companies. The chiplet package leverages SST’s SuperFlash technology, along with the interface logic and physical design elements required to function as a self-contained chiplet. This is paired with adaptive patterning-based redistribution layer (RDL) design rules, simulation flows, test strategies, and manufacturing paths through Deca’s ecosystem of qualified partners. Building on this foundation, Deca and SST will jointly support customers from early design through qualification and prototype manufacturing. By streamlining integration and accelerating design cycles, the companies aim to enable broader adoption of heterogeneous integration, engaging with customers globally to bring chiplet solutions to market. For more information, visit sst.com. SOLDER SOLUTIONS FOR EV AND ELECTRONICS Indium Corp., a leading materials refiner, smelter, manufacturer, and supplier to the global electronics, semiconductor, electric vehicle (EV), thin-film, and thermal Deca and Silicon Storage Technology collaborate on NVM chiplet solutions.
RkJQdWJsaXNoZXIy MTYyMzk3NQ==