November 2025_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 14 AVOIDING SEM-INDUCED DEVICE DEGRADATION THROUGH SEMI-BLIND NANOPROBING Marc Heinemann and Markus Reichel SmarAct Metrology GmbH & Co. KG, Oldenburg, Germany heinemann@smaract.com EDFAAO (2025) 4:14-20 1537-0755/$19.00 ©ASM International® INTRODUCTION Nanoprobing, particularly nanoprobing employed inside scanning electron microscopy (SEM), is an indispensable tool for inspection and failure analysis in semiconductor research and manufacturing. As technology nodes have scaled into the deep sub-10 nm regime, with 5 nm FinFETs and beyond now in production, the interaction between electron beams and nanoscale transistor structures has become a topic of growing concern. While SEM provides unrivaled resolution and defect detection capabilities, its high-energy electron exposure can alter material and electrical properties of sensitive device structures, potentially inducing degradation or permanent damage.[1] The physical mechanisms underlying e-beam-induced degradation are multifaceted. Primary interactions include charging effects in insulating and high-k dielectrics and the generation of defect states within oxide layers.[2] Even at relatively low landing energies typical of SEM imaging, charge trapping at the gate dielectric or interfacial layers can lead to measurable threshold voltage shifts, leakage paths, or instability in device operation.[3] This is particularly critical for advanced nodes, where ultra-thin oxides and reduced critical charges render devices more susceptible to perturbation. Despite these known risks, systematic data for the impact of SEM exposure, especially exposure time, on modern technology nodes remain sparse in the open literature, with much knowledge held in proprietary process and inspection recipes. Nevertheless, a consensus is emerging: Electron beam inspection must balance SEM image quality against the risk of device degradation, with low-energy operation and minimized dwell times increasingly recognized as essential safeguards. As industry pushes toward 5 nm, 3 nm, and gate-all-around (GAAFET) architectures, this trade-off is impractical and this article shows how to maintain high image quality while avoiding device degradation. 22 nm FD-SOI TECHNOLOGY To study the effect of beam-induced degradation, the authors chose to analyze the fully depleted silicon-oninsulator (FD-SOI) technology at the 22 nm node, as it is known to be highly sensitive to electron beam irradiation. The technology has attracted considerable interest due to its excellent electrostatic control, reduced short-channel effects, and body-biasing capability, making it suitable for low-power and RF applications. However, the very features that enable its performance advantages also render it highly sensitive to electron beam irradiation, such as that encountered during scanning electron microscopy (SEM) inspection and nanoprobing analysis. The defining characteristic of FD-SOI devices is the presence of an ultra-thin silicon film fully depleted over a buried oxide (BOX) layer (see Fig. 1). The BOX electrically isolates the transistor channel from the substrate. When exposed to electron beams, the BOX is particularly prone to charge trapping, because of its insulating nature and relatively high defect density compared to crystalline silicon. Electrons injected by the SEM can become trapped in the BOX or at the Si/BOX interface, leading to significant perturbations of the device’s electrostatics. Unlike bulk CMOS, where charge may be partially dissipated into the substrate, FD-SOI devices accumulate charge in the BOX region, resulting in large threshold voltage shifts and altered subthreshold slopes.[4] At the 22 nm node, gate stacks employ ultra-thin high-k/metal-gate dielectrics, often below 2 nm equivalent oxide thickness. This scaling further reduces the tolerance for trapped charge before functional degradation occurs. Furthermore, e-beam-induced degradation mechanisms in FD-SOI also raise reliability concerns under repeated exposure, because trapped BOX charges can persist for

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