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A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS PAGE 45 2024 WINNERS NOVEMBER 2025 | VOLUME 27 | ISSUE 4 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org CHIPLET ARCHITECTURES FOR SCALABLE INTEGRATION AVOIDING DEVICE DEGRADATION THROUGH NANOPROBING FA CHATBOT WITH RETRIEVAL- AUGMENTED GENERATION THERMAL APPROACHES TO FAULT ISOLATION IN 3D STRUCTURES 2 14 4 22

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS PAGE 45 2024 WINNERS NOVEMBER 2025 | VOLUME 27 | ISSUE 4 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org CHIPLET ARCHITECTURES FOR SCALABLE INTEGRATION AVOIDING DEVICE DEGRADATION THROUGH NANOPROBING FA CHATBOT WITH RETRIEVAL- AUGMENTED GENERATION THERMAL APPROACHES TO FAULT ISOLATION IN 3D STRUCTURES 2 14 4 22

edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 ABOUT THE COVER See page 45 for a description of the contest images collage on the cover. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS NOVEMBER 2025 | VOLUME 27 | ISSUE 4 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Avoiding SEM-induced Device Degradation Through Semi-blind Nanoprobing Marc Heinemann and Markus Reichel A semi-blind probe positioning approach effectively avoids beam-induced degradation by reducing the number of SEM images required. Author Guidelines Author guidelines and a sample article are available at edfas. org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 14 2 GUEST EDITORIAL Raja Swaminathan 32 CAM WORKSHOP SUMMARY Michael DiBattista 34 EDFAS AWARDS 35 ASM AWARDS 36 CALL FOR PAPERS 37 ISTFA 2025 EXHIBITORS LIST 38 ISTFA 2025 EXHIBITOR SHOWCASE 40 BOARD CANDIDATE PROFILES Felix Beaudoin 42 DIRECTORY OF FA PROVIDERS Rosalinda Ring 44 EDUCATION NEWS Navid Asadi 45 ABOUT THE COVER 46 LITERATURE REVIEW Michael R. Bruce 48 PRODUCT NEWS Ted Kolasa 50 TRAINING CALENDAR Rosalinda Ring 52 GUEST COLUMN Vinod Narang 54 GUEST COLUMN Lun Chan 56 ADVERTISERS INDEX Toward a Failure Analysis Chatbot with Retrieval-augmented Generation Maik Fichtenkamm, Markus Kofler, Konstantin Schekotihin, and Christian Burmer This article looks at naive, advanced, and modular retrievalaugmented generation architectures for an FA chatbot implementation. 22 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Innovative Thermal Approaches to Fault Isolation in Three-dimensional Semiconductor Structures Norimichi Chinone and Shimpei Tominaga Optical fault isolation techniques relying on heat diffusion, including thermo-reflectance and lock-in OBIRCH, are applied to relatively thin 3D devices as proof-of-concept test samples for FA applications. 14 4 22

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 2 The semiconductor industry is at a pivotal inflection point. As traditional transistor scaling slows and Moore’s Law faces economic and physical headwinds to enable next generation AI architectures, chiplets and heterogeneous integration technologies, including advanced packaging, have emerged as a foundational strategy for sustaining the growth of datacenter and edge AI applications. These modular designs are not just a workaround, they represent a paradigm shift in how we architect, manufacture, and scale silicon systems for AI enablement. Chiplets enable heterogeneous integration, allowing specialized dies— compute, memory, I/O—to be combined into a unified system. This modularity enhances design flexibility, improves yield, and accelerates innovation cycles. At AMD, we’ve seen firsthand how chiplet-based systems can meet the surging demand for compute, which is almost doubling every year—outpacing the transistor density gains of Moore’s Law. It’s also allowing us to build next generation AI architectures not feasible with monolithic silicon. Yield dynamics also favor chiplets. Splitting a monolithic system on chip (SOC) into smaller dies improves wafer utilization and allows selective binning for performance tiers. This flexibility enables AMD to address diverse markets—from consumer desktops to data center accelerators—with tailored configurations. Central to this evolution is the convergence of system architecture and advanced packaging. Technologies such as 2.5D and 3D hybrid bonding are key architectural enablers. For example, AMD’s 3D V-Cache uses hybrid bonding to stack a 64 MB cache chiplet directly atop a 32 MB L3 cache, tripling capacity with minimal latency overhead. This innovation delivers up to 15% faster gaming performance and three times the L3 cache in server implementations, dramatically improving application throughput. The elevated fan-out bridge (EFB) architecture, introduced in AMD’s MI200 GPU, exemplifies how advanced packaging innovation drives perfor- mance. By elevating the silicon bridge die within the copper pillar shadow, AMD achieved better electrical behavior and manufacturability—critical for deploying tens of thousands of units in systems like the Frontier supercomputer. The pinnacle of this was our introduction of the 3.5D architecture combining best-in-class 3D hybrid bonding and 2.5D architectures as demonstrated in high volume with the MI300/MI355 AI accelerators, and will take a leap with the MI450 family. Looking ahead, 3D stacking will unlock new architectural possibilities: IP-on-IP stacking, macro-level slicing, and circuit-level integration. These innovations will enable beyond-Moore scaling and heterogeneous systems that were previously only feasible in supercomputers. But to realize this vision, NOVEMBER 2025 | VOLUME 27 | ISSUE 4 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL CHIPLET ARCHITECTURES: ENABLING SCALABLE INTEGRATION FOR THE AI ERA Raja Swaminathan, AMD raja.swaminathan@amd.com edfas.org (continued on page 47) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2025 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Swaminathan

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 4 EDFAAO (2025) 4:4-11 1537-0755/$19.00 ©ASM International® INNOVATIVE THERMAL APPROACHES TO FAULT ISOLATION IN THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES Norimichi Chinone1 and Shimpei Tominaga2 1Hamamatsu Corp., San Jose, California 2Hamamatsu Photonics KK, Japan nchinone@hamamatsu.com INTRODUCTION Semiconductor devices have been on a continuous march to deliver higher performance, which is great for consumers, but creates ongoing challenges for fault isolation. Device improvement has been achieved by scaling design rules and by extending the device structure into the z-axis.[1] 3D structures have a variety of types and a range of thicknesses. Stacked-die is one type of 3D structure, where multiple dies (i.e., memory dies) are stacked. High bandwidth memory (HBM) is a another leading example of stacked-die with a thickness of 700 µm.[2] In HBM, each die is connected by through-silicon vias (TSVs) and micro-bumps.[2] 3D NAND flash memories became a major category of 3D structures in the last decade, displacing planar NAND flash memories.[3] A 3D NAND memory cell has hundreds of layers of word-line/insulator stacks that form vertically connected non-volatile memory cells, of which the total thickness can range from single digits to 10 µm.[3,4] Moreover, 3D NAND flash memories have increased the number of layers and stacked the cell on peripheral control logic,[5] which is referred to as cellover-peri (COP), CMOS under array (CUA), or 4D-NAND, depending on the manufacturer. Metal interconnects in Si wafers also form 3D structures with total thicknesses of single digits to 10 µm but they used to be on one side of the wafer only. Recent developments suggest backside metallization is going to be introduced, where power delivery network (PDN) and I/O network would be migrated to the backside (opposite of the active layer).[1] This novel structure is expected to provide relief in the metal interconnect density and voltage IR-drop.[6] However, this adds another challenge to FA because it blocks direct optical access to the active layer. To localize defects in these 3D-structured devices, the FA community has devoted much effort by using a variety of techniques including optical fault isolation (OFI), x-ray,[7] ultrasonic,[8] electron beam (EB),[9] and tera-hertz techniques.[10] As for OFI, techniques that rely on heat diffusion and magnetic field have gained attention because of their penetrative features. Thermal lock-in (LIT)[11] and optical-beam induced resistance change (OBIRCH)[12,13] or thermal induced voltage alteration (TIVA)[13] are major heat-relying OFI techniques. Because the latter two techniques are similar, this article focuses on OBIRCH. LIT images use modulated heat sources on the sample with a focal plane array that is sensitive to mid-infrared (MIR) and software lock-in operation.[14] The resulting images are generally used to find abnormal hotspots that may indicate short defect location. Because the LIT phase image contains in-depth information, studies have been done to localize the defect in the xyz space.[15] Generally, modulation frequency of LIT is less than 1 kHz and according to Nyquist-Shannon sampling theorem, it should be less than half of the frame rate. In this frequency range, relatively thick 3D structures such as stacked chips are the target. The theoretical background of this technique is discussed later. OBIRCH focuses a laser beam on a sample that is operated at constant voltage or current. The laser spot locally heats the sample, which causes a small perturbation in current or voltage if the heated location is temperature sensitive.[12,13] A raster scan of laser spots generates a map of temperature sensitive locations, which tends to indicate a short defect or abnormal metal trace confinement locations.[12] Lock-in (LI) OBIRCH is a variant of this technique, where the stimulation laser beam is pulsed at certain frequency and the resulting current/voltage perturbation is lock-in detected.[16,17] This technique improves the signal-to-noise ratio by an order of magnitude. In the Hamamatsu tool, laser modulation frequency covers sub-kHz to over 100 kHz, which can correspond to

edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 thickness of relatively thin 3D structures such as 3D NAND flash and backside metallized devices. Another technique, thermo-reflectance (TR),[18-20] has started to gain attention in the FA community because of its potentially higher spatial resolution compared to LIT by means of shorter probing beam wavelength and higher modulation frequency of kHz to MHz range, which makes the technique a candidate for relatively thin 3D structures such as 3D NAND flash and BS-PDN devices. This article focuses on the latter two techniques, and technical details including working principles, performance, limitations, as well as future perspectives, are discussed. THEORY OF HEAT DIFFUSION Both TR and LI-OBIRCH techniques rely on heat diffusion, but they measure different physical properties of the sample. A key distinction lies in their heat sources: in TR, heat is generated internally within the sample, whereas in LI-OBIRCH, the laser spot serves as the external heat source. To better understand the behavior and effectiveness of these methods, it is useful to briefly review the principles of heat diffusion. Temperature, T, in isotropic and uniform medium is described by the well-known second order derivative equation: (Eq 1) where κ, ρ, and c are thermal conductivity, density, specific heat capacity of the medium, respectively. Consider a point heat source at the origin of coordinate in the medium. At the same time, the heat source is modulated at frequency, f, (or angular frequency of ω = 2πf ). A quasisteady state solution of the temperature field outside of the heat source, which satisfies Eq. 1, is obtained by omitting the time-dependent term ejwt: (Eq 2) where , and j is a unit of imaginary number. A is a constant complex number, which denotes the amplitude and phase of heat source temperature and is determined by heat source power and modulation frequency. Equation 2 can be broken down to amplitude and phase expression as follows: (Eq 3) Equation 3 means that thermal diffusion length and phase is proportional to and distance. Table 1 summarizes ld for some materials and frequencies. Thermal properties were cited from references 21 and 22. One can notice that heat diffusion in SiO2 is 10 times worse than Si. When layers of Si and SiO2 are stacked, for example, heat diffusion in stacked axis is dominated by SiO2. For single digit µm thickness, 10 to 100 kHz would be available, while 100 Hz to 10 kHz would be required to measure two digits of µm range. Although Eq 2 is valid just for a point heat source, it’s worth noting that Eq 2 is quite useful because convolving Eq 2 and heat source distribution gives a temperature field for general cases. For example, when the heat source is uniformly distributed in plane and its size is relatively smaller than or comparable to the z-dimension of interest, the expression of temperature field becomes (Eq 4) Heat source 0 otherwise which exactly matches a one-dimensional solution of Eq 1 with an infinite limit of heat source areas. Phase dependency against z is the same as Eq 3. THERMO-REFLECTANCE The authors’ TR technique, ThermoDynamic Imaging (TD Imaging), uses a focused low noise incoherent optical beam and laser scanning optics. Figure 1 shows the working principle and measurement system of TD Imaging, where a circuit with an anomaly or defect under a metal surface produces significant Joule heating when powered up, while the Joule heating in normal circuit is assumed to be negligible. A focused probing beam is used, and the reflected light power changes around the hotspot. TD Imaging uses fiber-coupled low noise incoherent light sources (high intensity lasers or HILs, Hamamatsu Photonics K.K.) as a probing beam. The probing beam is guided to the sample surface via scanning optics, with some portion reflected back. Pin represents the incident Table 1 Thermal diffusion length of Si and SiO2 at frequencies of 100 Hz to 100 kHz[21,22] Medium and thermal properties (ρ, c, κ) ld at 100 Hz ld at 1 kHz ld at 10 kHz ld at 100 kHz Si (2330 kg/m3, 703 J/kgK, 126 W/mK)[21] 540 µm 170 µm 54 µm 17 µm SiO2 (2200 kg/m3, 745 J/kgK, 1.38 W/mK)[22] 52 µm 16 µm 5.2 µm 1.6 µm

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 6 beam power at sample surface. Reflected beam power Pr is then given by: Pr = R(T)Pin (Eq 5) where R(T) is temperature-dependent reflectance at given wavelength. When the temperature varies by ∆T(t) over time, t, the material’s reflectance changes, resulting in a corresponding change in the reflected beam power, denoted as ∆Pr. For example, when the sample is electrically modulated at angular frequency, ω, the temperature change is expressed as ∆T(jwt + j), where t and j are time and an imaginary unit, respectively. j represents timing difference relative to the timing of exercising the device. Then Eq 5 is rewritten as: (Eq 6) Lock-in detection of ∆Pr(t) with a reference signal from the sample exercising apparatus provides an amplitude of and phase j. These are collected by a computer and mapped two-dimensionally by raster scanning the probing beam. The resulting images are called TD Imaging amplitude and phase image. Alternatively, the operation of amplitude × cos cos phase generates an in-phase image. The sensitivity of TD Imaging is calculated by dividing the reflected beam power changes ∆Pr by the reflected beam power Pr. (Eq 7) The thermo-reflectance coefficient (TR Coeff) depends on the material and wavelength. In semiconductor devices, Al or Cu are commonly used for interconnects, and TR Coeffs are expected to be larger in the visible wavelength than in the infrared. Table 2 shows measured TR Coeff values of Al and Cu at two wavelengths in the lab with HIL values of 1300 nm and 670 nm. The temperature modulation, expressed as increases when electrically modulated at a lower angular frequency ω. As a result, TD imaging systems are optimally compatible with low-frequency modulation. However, the frequency is limited because there is noise when the probing beam is vibrating slightly. Figure 2 is the amplitude image of TD Imaging using the optics chart Fig. 1 Working principle and experimental system setup of TD Imaging. A circuit biased with a periodic current with an interconnect anomaly is buried under the metal surface. The periodic current induces significant Joule heating at the confinement anomaly, while other sections of the interconnect remain unaffected. This localized heating modulates the optical reflectance in the vicinity of the anomaly. One of 1300 nm and 670 nm HILs is focused on sample surface, and the reflected beam is guided to APD. The photocurrent of APD is lock-in detection with reference signal provided by pulse generator. Amplitude and phase measured by lock-in amplifier are recorded in a computer as pixel intensity. Table 2 Comparison of TR Coeff values of Al and Cu at two wavelengths in this system Wavelength of Light Source |TR Coeff, ppm/K| Cu Al 670 nm 20 50 1300 nm 10 20

edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 when the frequency was set to 5 kHz. Strong signals are observed along the outline of the pattern. This is unnecessary noise (called scan noise) because it is not a signal of thermo-reflectance. In the case of 670 nm, the scan noise level is high, in the range of 1 to 10 kHz. Above 10 kHz, the scan noise level drops to the floor level of the light source. Regarding the detection limit of the TD Imaging system, noise equivalent temperature (NET) is of significant interest. ∆Pr is converted to photocurrent I by an avalanche photodiode (APD), then Eq 7 is rewritten as: (Eq 8) NET depends on the system, the sample surface material, its structure, and condition of the surface. Another general parameter to characterize the system would be the relative noise equivalent photocurrent (RNEP), which is calculated by dividing noise equivalent photocurrent ∆I by DC photocurrent I flowing through the APD. RNEP is ultimately limited by relative intensity noise (RIN) of light source. Table 3 shows the RNEP and NET in 670 nm and 1300 nm HILs. This is calculated by the TR Coeff in Table 2, and ω is 100 kHz. PROOF-OF-CONCEPT EXPERIMENT To test the capability of TD Imaging, a simple test structure fabricated with an 8 μm-wide Al wire (resistance = and ω is 100 kHz. PROOF-OF-CONCEPT EXPERIMENT To test the capability of TD Imaging, a simple test structure fabricated with an 8 μm- wide Al wire (resistance = 5.6 ohm) is shown in Fig. 3a. Significant Joule heating is expected at this wire. For modulating the heat, a square wave bias with a voltage swing of 0 to 210 mV at certain frequencies was applied to the sample. This sample was analyzed with the TD Imaging tool, first with the 1300 nm, then with 670 nm light sources. Modulation frequencies were set at 8 kHz. A Mitutoyo objective lens of 20× with a numerical aperture (NA) of 0.40, is transparent enough to see the two wavelengths. Multiple probing beam powers of no higher than 1.0 mW were used on the sample. TD Imaging in phase images with 670 nm and 1300 nm light source at probing beam power of 1.0 mW is shown in Figs. 3b and c, respectively, where pixel color indicates amount of perturbation in the reflected beam power or ∆Pr. To quantitatively compare the results among the techniques, the team evaluated signal-to-noise ratio (SNR). Figure 4 compares SNR of TD Imaging results with 1300 nm and 670 nm as a function of probing beam power. The dotted red circle symbol and dotted blue rectangular symbol shows data points with 670 nm and 1300 nm, respectively. For both light sources, a region is reached Fig. 2 Scan noise of the optics chart. (a) Pattern image. (b) TD Imaging amplitude. Magnification is 20×. The light source is 670 nm HIL. (a) (b) Table 3 Comparison of RNEP and NET of Al and Cu at two wavelengths in this system Wavelength of light source RNEP, db/Hz NET, mk/√Hz Cu Al 670 nm -135 8 3 1300 nm -145 5 5 Fig. 3 Pattern and TD Imaging in phase images of the test sample. (a) Infrared laser reflection image. The magnification is 20× × 4× zoom. 8-μm-wide Al wire is deposited on Si/SiO2 substrate. (b) and (c) TD Imaging in phase images with 670 nm and 1300 nm HILs. (a) (b) (c)

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 8 where SNR does not change as the probing beam power increases. CHALLENGES AND FUTURE PERSPECTIVE There are three primary challenges associated with TD Imaging. The first is the expansion of the light source wavelength. It is desirable to have a light source with selectable wavelengths because TR Coeff depends on the sample material and structure. The second is the scan noise. In laser scanning optics, scan noise occurs at low frequency, so reducing this noise is important. The last one is RIN of the light source. RIN is a parameter that limits the sensitivity of TD Imaging, therefore a more stable light is required. LI-OBIRCH LI-OBIRCH[16,17] is a variant of OBIRCH,[12] which is used for finding temperature sensitive defects by means of laser heating.[12] A typical setup for LI-OBIRCH is illustrated in Fig. 5. A constant bias voltage is applied to the sample, which, for this example, consists of three distinct layers. The bottom layer is directly heated by a laser beam and the upper layers are indirectly heated via heat diffusion, which causes a small perturbation in current. Current perturbation is monitored typically by an AC-sensitive transimpedance amplifier, whose output is fed into a lock-in amplifier.[17] The laser beam spot position is scanned by laser scanning optics. While the beam is scanned, the beam is pulsed or modulated at a certain frequency.[16,17] A reference signal which synchronizes to the modulation is fed to the lock-in amplifier. The lock-in amplifier will yield the amplitude (R) and phase (θ) of the frequency component corresponding to the reference signal as shown in Fig. 5. Another representation of LI-OBIRCH data is in phase (I) and quadrature (Q) format, which is defined as I = R cos cos θ and Q = R sin sin θ. In LI-OBIRCH, the focused laser beam spot on the sample is the heat source and it is modulated by pulsing the laser at a frequency. Temperature field, which can be approximated by Eq 2, is generated around the laser beam spot. In LI-OBIRCH, the velocity of laser beam spot is set slow compared to laser modulation. With this condition, one can approximate that the temperature field moves with the laser beam spot without distorting its form. When the laser beam is focused on sample surface (z = 0) and lateral location (x', y'), the temperature field is simply Tw(x - x', y - y', z). For this discussion, uniform and anisotropic material is assumed, which is not actually realistic. However, this approximation is valid as the local structure’s dimension is very small. OBIRCH sensitivity distribution, γ(x,y,z), denotes how much OBIRCH signal is generated when temperature at (x,y,z) changes by unit temperature. Using γ(x,y,z) and temperature field expression, LI-OBIRCH signal at modulation angular frequency w, w(x,y), is derived by: (Eq 9) Fig. 4 Comparisons of TD Imaging SNR vs. probing beam power among different wavelength HILs. Fig. 5 Simplified diagram of the LI-OBIRCH system and interpretation of data.

edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 Assuming that laser spot size is comparable to the z-dimension, the expression in Eq 4 can be used, and this will yield the following: (Eq 10) Collecting LI-OBIRCH data with multiple modulation frequency will enable one to find γ(x,y,z), which best approximates the collected data set by means of some optimization algorithm. Further details on this algorithm can be found in reference 17. PROOF-OF-CONCEPT EXPERIMENT A proof-of-concept experiment to test the developed algorithm was carried out on a Hamamatsu FA tool, PHEMOS. An LI-OBIRCH system can be implemented on a single system as well as other OFI functionalities. The test vehicle is illustrated in Fig. 6. Aluminum is deposited on SiO2/Si substrate, which forms a simple circuit and isolated metal dot.[17] When the laser spot stays on the metal trace, the biased trace is directly heated, which simulates the bottom layer. On the other hand, when the laser spot is on the isolated metal dot, biased trace is heated via heat diffusion, which simulates the top layer. Figure 7a shows the laser reflection image and Fig. 7b shows the in-phase and quadrature LI-OBIRCH images with multiple laser modulation frequencies. The collected LI-OBIRCH dataset was processed using the team’s algorithm, resulting in images that correspond to different depths within the sample. In this proof-of-concept test, the “depth” technically does not mean physical depth, instead, direct heating or indirect heating is interpreted as different depths.[17] Figures 8a-c show the laser reflection image (shown again), lower layer image, and higher layer image, respectively. The signal obtained on the isolated metal dot is more pronounced in the higher layer image while the signal on metal trace is more pronounced in the lower layer image, meaning that the algorithm assigned signals to different depths. CHALLENGES AND FUTURE PERSPECTIVE The first challenge for this technique is exponential signal decay against depth as previously discussed. Using lower modulation frequency mitigates this signal decay, however, at lower frequencies, more heat diffusion degrades the lateral spatial resolution of the technique. Fig. 6 Structure of the proof-of-concept test sample. Al is deposited on SiO2 and the Si substrate, which forms a metal trace and an isolated metal island. Fig. 7 Laser reflection image and LI-OBIRCH images collected on the proof-of-concept test sample. (a) Laser reflection image. (b) LI-OBIRCH images (in-phase and quadrature) with different frequencies between 0.625 and 20 kHz. (a) (b)

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 10 Some improvements that can mitigate this trade-off will be required to extend the LI-OBIRCH technique to thicker (~10 µm or more) devices. The second challenge is the data processing algorithm. To get reasonable processing results, parameters need to be tuned and the FA engineers have to iterate an analysis several times. Besides, approximated temperature field and uniform medium approximation can cause additional errors. Further algorithm and GUI improvement will be required. At the same time, exploring applicable cases using real customer field samples is also quite important to understand better the benefits and drawbacks of the technique and algorithm. SUMMARY OFI techniques for FA applications relying on heat diffusion were discussed for 3D devices. Using relatively thin 3D devices as proof-of-concept test samples, the TR and LI-OBIRCH techniques were discussed, with a brief reference to heat diffusion theory. In the section for TR, the working principle of the technique and simple testing capability of TD Imaging were discussed. TR Coeff is different depending on the sample structure. TD Imaging has been enhanced to allow selection of any wavelength for probing. It is also important to reduce the noise of the light source (RIN). In the LI-OBIRCH section, the working principle of the technique and a simple mathematical model for 3D analysis were discussed, along with experimental results from proof-of-concept tests, which confirmed the promise of the team’s 3D data processing algorithm. Physics-related challenges and algorithm challenges were also discussed. TR and LI-OBIRCH can be promising OFI candidates for 3D devices such as BS-PDN and 3D NAND flash memories. Hamamatsu will continue advancing failure analysis for 3D and next-generation devices, contributing to the development of future FA techniques. ACKNOWLEDGMENTS The authors would like to acknowledge Dr. Tomonori Nakamura, Mitsunori Nishizawa, Yuji Nakajima, Mitsuyoshi Yoneda, Xiangguang Mao, Yuhei Aoshima, Shinsuke Suzuki, Yukako Tabuchi, Masataka Ikesu from Hamamatsu Photonics K.K., for designing low noise light sources, low noise scanner, designing system, and software. REFERENCES 1. “More Moore,” IEEE International Roadmap for Devices and Systems (IRDS) 2023 Update, IEEE, 2023. 2. “High Bandwidth Memory (HBM3) DRAM,” JEDEC, Apr. 2025. 3. “Mass Data Storage,” IEEE International Roadmap for Devices and Systems (IRDS) 2023 Update, IEEE, 2023. 4. Y. Wang, et al.: “3D NAND Oxide/Nitride Tier Stack Thickness Measurements with Infrared Metrology,” 2023 34th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2023, p. 1-8. 5. P. Kalavade: “4 bits/cell 96 Layer Floating Gate 3D NAND with CMOS under Array Technology and SSDs,” 2020 IEEE International Memory Workshop (IMW), Dresden, Germany, 2020, p. 1-4. 6. M.J. Kobrinsky, et al.: “Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking,” IEDM2023. 7. W. Lo: “X-Ray Device Alteration using a Scanning X-Ray Microscope,” Proceedings of the ISTFA2022, 2022, p. 153-162. 8. T. Matsumoto: “Ultrasonic Beam Induced Resistance Change,” EDFA, 20(3), 2018, p. 18-22. 9. J.J. Huening, et al.: “E-beam Probing and E-beam-Assisted Device Alteration (EADA) for Fault Isolation in PowerVia and Advanced Technology Nodes,” Proceedings of the ISTFA2024, 2024, p. 519-522. 10. C. Zhang, et al.: “High-Precision Pulse Reflectometry-Based Fault Localization Approach for Advanced Chip Package Failures,” Proceedings of the ISTFA2023, 2023, p. 285-290. 11. C. Schmidt, et al.: “Application of Lock-in Thermography for Failure Analysis in Integrated Circuits using Quantitative Phase Shift Analysis,” Mat. Sci. and Eng. B, 177, 2012, p. 1261. 12. K. Nikawa, et al.: “Novel Method for Defect Detection in Al Stripes by Means of Laser Beam Heating and Detection of Change in Electrical Resistance,” Jpn. J. Appl. Phys., 34, 1995, p. 2260. 13. D.K. Shroder: “Semiconductor Material and Device Characterization,” 3rd edition, IEEE Press, Wiley-Interscience, p. 721-722. 14. O. Breitenstein et al.: “Lock-in Thermography Basics and Use for Evaluating Electronic Devices and Materials,” Springer, 2nd Edition, 2010. 15. C. Schmidt, et al.: “Application of Lock-in Thermography for Failure Analysis in Integrated Circuits using Quantitative Phase Shift Analysis,” Mat. Sci. and Eng. B, 177, 2012, p. 1261. 16. K.J.P. Jacobs, et al.: “Lock-in Thermal Laser Stimulation for Nondestructive Failure Localization in 3-D Devices,” Microelectronics Reliability, 76-77, 2017, p. 188. 17. N. Chinone, et al.: “Concept-Proof of Lock-in OBIRCH Application Fig. 8 Laser reflection image and processed results. (a) Laser reflection image. (b) and (c) Data processing results which correspond to “bottom” and “top,” respectively. (b) (c) (a)

edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 for Three-Dimensional Analysis of Four-Dimensional NAND Flash Memory,” Proceedings of the ISTFA2024, 2024, p. 327-331. 18. D. Kendig: “Thermal Imaging Based on Thermoreflectance Ad- dressing the Challenges for Thermal Analysis of Today’s Advanced Complex Devices,” ICEPT, 2016. 19. K. Endo, et al.: “Thermal Behavior Analysis of Interconnect Structures of Si Semiconductor Devices using the Temperature Dependent Reflectance of an Incoherent Light Beam,” Jpn. J. Appl. Phys., 54, 2018, 07ME02. 20. S. Tominaga, et al.: “Application of Visible ThermoDynamic Imaging Technology for Hotspot Detection in Failure Analysis,” Proceedings of the ISTFA2024, 2024, p. 242-247. 21. TPSX Material Properties Database, Silicon. 22. TPSX Material Properties Database, Silicon Oxide. ABOUT THE AUTHORS Norimichi Chinone received a doctor of engineering degree from Tohoku University, Japan, in 2017. After graduation, he started working at Hamamatsu Photonics for R&D on the failure analysis microscope system, PHEMOS. Since 2023 he has worked at Hamamatsu Corp. in the USA as an application engineer for PHEMOS. His research interest includes OBIRCH, time-resolved emission, and magnetic field imaging. Shimpei Tominaga received his bachelor’s degree in science from Shinshu University. He joined Hamamatsu Photonics K.K. in 2017 as an application engineer of semiconductor failure analysis. Since 2022, he has been in the R&D Group System Technology Systems Division to develop failure analysis equipment. He focuses on failure analysis for advanced devices such as BS-PDN where active layer is sandwiched by signal metal layers and power metal layers. Tominaga has been a speaker at several semiconductor conferences (ISTFA, CAM Workshop, etc.) and coauthored several articles and patents. EDFAS members enjoy these benefits: • Subscription to the Electronic Device Failure Analysis (EDFA) magazine • Subscription to the EDFA eNews • Online access to EDFA magazine articles • Online access to the Journal of Failure Analysis and Prevention (JFAP) • Online access to the 7th Edition Microelectronic Failure Analysis Desk Reference • Online access to all International Symposium for Testing and Failure Analysis (ISTFA) proceedings • Access to the EDFAS Membership Directory • Discount on registration for the annual ISTFA Conference and Exposition EDFAS, the Electronic Device Failure Analysis Society, focuses specifically on the reliability, testing, and failures of circuits, semiconductors, and other electronics platforms. SHAPE THE FUTURE OF YOUR CAREER FOR MORE INFORMATION: memberservicecenter@asminternational.org 440.671.3800 JOIN ONLINE: EDFAS.ORG

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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 14 AVOIDING SEM-INDUCED DEVICE DEGRADATION THROUGH SEMI-BLIND NANOPROBING Marc Heinemann and Markus Reichel SmarAct Metrology GmbH & Co. KG, Oldenburg, Germany heinemann@smaract.com EDFAAO (2025) 4:14-20 1537-0755/$19.00 ©ASM International® INTRODUCTION Nanoprobing, particularly nanoprobing employed inside scanning electron microscopy (SEM), is an indispensable tool for inspection and failure analysis in semiconductor research and manufacturing. As technology nodes have scaled into the deep sub-10 nm regime, with 5 nm FinFETs and beyond now in production, the interaction between electron beams and nanoscale transistor structures has become a topic of growing concern. While SEM provides unrivaled resolution and defect detection capabilities, its high-energy electron exposure can alter material and electrical properties of sensitive device structures, potentially inducing degradation or permanent damage.[1] The physical mechanisms underlying e-beam-induced degradation are multifaceted. Primary interactions include charging effects in insulating and high-k dielectrics and the generation of defect states within oxide layers.[2] Even at relatively low landing energies typical of SEM imaging, charge trapping at the gate dielectric or interfacial layers can lead to measurable threshold voltage shifts, leakage paths, or instability in device operation.[3] This is particularly critical for advanced nodes, where ultra-thin oxides and reduced critical charges render devices more susceptible to perturbation. Despite these known risks, systematic data for the impact of SEM exposure, especially exposure time, on modern technology nodes remain sparse in the open literature, with much knowledge held in proprietary process and inspection recipes. Nevertheless, a consensus is emerging: Electron beam inspection must balance SEM image quality against the risk of device degradation, with low-energy operation and minimized dwell times increasingly recognized as essential safeguards. As industry pushes toward 5 nm, 3 nm, and gate-all-around (GAAFET) architectures, this trade-off is impractical and this article shows how to maintain high image quality while avoiding device degradation. 22 nm FD-SOI TECHNOLOGY To study the effect of beam-induced degradation, the authors chose to analyze the fully depleted silicon-oninsulator (FD-SOI) technology at the 22 nm node, as it is known to be highly sensitive to electron beam irradiation. The technology has attracted considerable interest due to its excellent electrostatic control, reduced short-channel effects, and body-biasing capability, making it suitable for low-power and RF applications. However, the very features that enable its performance advantages also render it highly sensitive to electron beam irradiation, such as that encountered during scanning electron microscopy (SEM) inspection and nanoprobing analysis. The defining characteristic of FD-SOI devices is the presence of an ultra-thin silicon film fully depleted over a buried oxide (BOX) layer (see Fig. 1). The BOX electrically isolates the transistor channel from the substrate. When exposed to electron beams, the BOX is particularly prone to charge trapping, because of its insulating nature and relatively high defect density compared to crystalline silicon. Electrons injected by the SEM can become trapped in the BOX or at the Si/BOX interface, leading to significant perturbations of the device’s electrostatics. Unlike bulk CMOS, where charge may be partially dissipated into the substrate, FD-SOI devices accumulate charge in the BOX region, resulting in large threshold voltage shifts and altered subthreshold slopes.[4] At the 22 nm node, gate stacks employ ultra-thin high-k/metal-gate dielectrics, often below 2 nm equivalent oxide thickness. This scaling further reduces the tolerance for trapped charge before functional degradation occurs. Furthermore, e-beam-induced degradation mechanisms in FD-SOI also raise reliability concerns under repeated exposure, because trapped BOX charges can persist for

edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 long timescales, effectively “remembering” the irradiation history.[5] HOW TO AVOID SEM-INDUCED DEGRADATION This study not only investigates the degradation caused by SEM but also looks at ways to reduce or even prevent it. This is done by optimizing the SEM parameters, the tungsten probes, and the nanoprobe itself. These three factors are examined below. OPTIMIZATION OF SEM PARAMETERS The most direct means of reducing electron-induced degradation is through careful selection of beam parameters: • Lower landing energy: Reducing the accelerating voltage (e.g., to 100 to 200 eV) minimizes penetration depth and reduces charging in buried layers, while still providing surface-sensitive imaging.[6] • Reduced probe current: Lower beam currents directly decrease electron dose per unit time, though at the cost of reduced signal-to-noise ratio. • Fast scanning and reduced dwell times: Shorter pixel dwell times and pixel integration strategies can limit localized charge buildup and minimize exposure of any one region.[3] Together, these settings help ensure that the cumulative dose remains below the critical threshold for inducing dielectric charging or trap creation. As technology nodes continue to shrink, dose management will become increasingly critical, and emerging solutions such as beam deceleration techniques may play a role in maintaining device integrity during high-resolution elec- tron microscopy. OPTIMIZING TUNGSTEN PROBES Nanoprobing under low accelerating voltages in the SEM presents unique challenges that lab engineers regularly face during fault analysis of advanced semiconductor devices. Standard tungsten probes, while mechanically robust and conductive, can introduce unexpected imaging distortions when operated below ~200 eV. This is primarily due to the paramagnetic nature of tungsten, which interacts with the SEM’s electron beam and amplifies the effects of even weak magnetic fields—leading to beam deflection, image drift, or degraded resolution, resulting in a distorted image. To maintain stability and precision in such sensitive conditions, specially prepared probe needles are required. These must be mechanically sharp and clean, as well as have a special geometry to minimize the magnetic interaction with the electron beam. Off-the-shelf needles often fail to meet these criteria, especially for high-precision contact on sub-10 nm structures. The example image (Fig. 2) shows such special low-eV tungsten probes, which have a greatly reduced amount of tungsten near the electron beam and cause only minimal image distortion even at 100 eV. In this study, the probes were produced with the SMARPROBE etching station, which can be installed directly next to any SEM to produce fresh probes oxide-free and free of contaminants.[7] OPTIMIZING NANOPROBING While the aforementioned parameters, such as optimized imaging conditions and reduced electron beam energies, undoubtedly contribute to a reduced beaminduced degradation, particularly under low-energy conditions. Another effective strategy for reducing cumulative electron dose during nanoprobing lies in minimizing the total number of required images at the point of interest. Conventionally, a typical nanoprobing workflow involves continuous SEM imaging throughout the alignment and positioning of probes, often spanning several minutes and generating hundreds of SEM frames. But how to reduce the image count during probing? Fundamentally, after the relative spatial positions of both the sample and the individual probes have been determined—e.g., via three-point alignment routines or Fig. 1 The degradation dynamics of 22 nm FD-SOI technology were investigated by varying the electron dose incident on the buried oxide layer. The total electron dose depends on the beam current, beam energy, and imaging time (scan speed and total number of images).

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 16 automated image-based recognition—it becomes theoretically feasible to navigate the system based solely on pre-defined coordinate data derived from the corresponding CAD layout. An example of this is shown in Fig. 3. Under ideal conditions, such a procedure would negate the need for active SEM monitoring during navigation. However, this approach is often not possible due to two principal limitations of most motion systems: (1) the absence or inadequacy of integrated nanometer-precise position sensors across all motion axes in standard probing systems, and (2) the challenge of safely landing delicate probe tips without real-time visual feedback, which risks mechanical damage to both probes and sample structures. SmarAct’s SMARPROBE nanoprobing platform was chosen to address the aforementioned challenges.[8] This system provides several critical advantages that substantially reduce electron beam exposure and enhance probing reliability. First, the integration of fully encoded nanosensors enables navigation to predefined points of interest (POIs) solely by coordinate data, thereby eliminating the need for continuous SEM imaging during probe movement. Second, the system’s automated landing routines allow safe probe placement on both conductive and insulating surfaces without requiring visual feedback. Third, closed-loop control with active compensation corrects for intrinsic limitations of piezo-driven actuators, Fig. 2 Probing at 100 eV is more difficult due to stronger image distortion and shadowing induced by the probes. Special low-eV probes from the SMARPROBE etching station reduce but do not completely eliminate these effects. Fig. 3 Position of probes and sample can be set via three-point alignment routines and automated probe recognition. Relevant interconnects for the probing process are imported into the SMARPROBE user interface and superimposed on the SEM image. The positions of the probes are shown in yellow.

edfas.org 17 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 such as creep and hysteresis, ensuring stable long-term positioning. Finally, the control software supports seamless correlation of SEM images with the device CAD layout, enabling automated alignment and direct probe contact to the targeted transistor structures. Collectively, these features allow for efficient, low-dose, and highly reproducible nanoprobing of advanced semiconductor devices. These features converge in what the authors refer to as semi-blind positioning: a novel operational paradigm in which probes are navigated based on high-resolution position data rather than continuous visual feedback. But why “semi-blind?” While motion operations are no longer reliant on real-time SEM feedback, verification of the final probe position is still reasonable. Thus, imaging is performed discretely—typically at key checkpoints. For example, an initial SEM frame (acquired at 200 eV with a frame time of 120 ms) is used for CAD-based targeting (see Fig. 3) or probe positioning via point-and-click (see Fig. 4). After the target is reached, a follow-up frame verifies accurate probe placement. With active position-holding and drift suppression, no intermediate images are needed. Using the semi-blind positioning, it is possible to contact a transistor with six discrete movements, resulting in six SEM images. While using probing with visual feedback, the contacting of a transistor takes a few minutes, resulting in hundreds of images. RESULTS FROM SEMI-BLIND NANOPROBING To systematically investigate the extent of electron beam-induced degradation in beam-sensitive technologies, a controlled experiment was designed using a fieldeffect transistor (FET) implemented in a 22 nm FD-SOI technology node. The experimental setup consists of the SmarAct SMARPROBE nanoprobe, a Carl Zeiss Sigma 300 SEM, and a Keithley Parameter Analyzer 4200A (Fig. 5). The FD-SOI architecture was chosen, as it is known to exhibit increased susceptibility to radiation-induced degradation. As a reference, a pristine pFET device was first characterized without any exposure to the electron beam, using an atomic force probe (AFP), which allows electrical characterization in ambient conditions with zero e-beam interaction. This measurement provided baseline parameters, most notably the threshold voltage (Vth), derived from I–V characteristics, against which all subsequent measurements could be compared. Following the baseline measurement, the same device was characterized using SmarAct’s SMARPROBE Fig. 4 The probes can be positioned manually using point and click. Because there are no parasitic movements due to piezo creep, one image per movement is sufficient as visual feedback. Fig. 5 SEM-based nanoprobing combines the advantage of accurate probe placement and e-beam analysis techniques like electron beam induced current (EBIC). This picture shows the experimental setup based on the SMARPROBE nanoprobe.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 4 18 nanoprobing platform, employing its semi-blind positioning capability to minimize the number of SEM exposures during probe alignment, sample navigation, and probe contacting. In this mode, only six SEM images at the point of interest were acquired during the probe landing procedure, each confined to a 1 μm × 1 μm field of view, with an imaging time of 120 ms per frame. To minimize irradiation effects, the SEM was operated at a low beam current of 20 pA and an accelerating voltage of 100 eV. The resulting electrical characteristics, specifically the threshold voltage, were then directly compared to the AFP baseline. Despite slight device-to-device variations (± 5%), no significant deviation in threshold voltage was detected, indicating that the minimal SEM exposure associated with semi-blind positioning does not induce observable degradation under these operating conditions. To probe the onset and dynamics of degradation, a follow-up experiment involved continuous SEM exposure on the same 1 μm² area under identical beam current conditions but varying beam energies. The evolution of the threshold voltage over time was monitored, normalized to the value obtained after semi-blind contacting (see Fig. 6). During this time, the SMARPROBE was in constant electrical contact with the pFET, and the contact resistance to the probes remained constant throughout. Although not shown in the figure, immediate and severe threshold shifts were observed at 500 eV, suggesting aggressive charge injection and/or defect activation in the gate oxide. At lower energies—200 eV and 100 eV—the degradation kinetics were substantially slower; however, observable threshold voltage shifts still emerged within the first 60 seconds of continuous exposure. The effect was notably more pronounced at 200 eV, where degradation occurred at approximately eight times the rate observed at 100 eV. Interestingly, the degradation profiles exhibited a near-linear evolution with time at both beam energies, indicating that the underlying physical mechanism— presumed to be charge trapping in the BOX or gate oxide layers—does not saturate within the timescale of observation. Moreover, the threshold shifts were not reversible even after several days. While the slower degradation observed at 100 eV is beneficial, it comes at a significant trade-off: Image quality at this energy level is substantially compromised due to reduced signal-to-noise ratio, image distortion, and strong shadowing from the probes. Consequently, the lower imaging fidelity at 100 eV necessitates longer acquisition times or repeated imaging to achieve sufficient contrast for probe placement. If, for instance, probing at 100 eV takes eight times longer than at 200 eV, the cumulative beam dose and thus the degradation risk may equal—or even exceed—that at 200 eV. This leads to an important insight: In practical probing workflows, minimizing the number of SEM images can be more effective for reducing electron beam-induced damage than merely lowering the beam energy. The semi-blind positioning approach reduces the required number of SEM images by approximately two orders of magnitude compared to manual probe landing. The total electron dose at 200 eV in semi-blind mode is estimated to be at least 10 times lower than during manual probing at 100 eV. This estimation aligns with the empirical data: When using semi-blind positioning at 200 eV, no degradation was observed, and the electrical parameters remained consistent with the AFP benchmark. This is especially important for SEM models that perform poorly in the low eV range. Furthermore, in many applications, it is necessary to probe all six transistors of a standard 6T SRAM cell, which significantly increases cumulative beam exposure during manual probing. If conventional, visually guided methods are used, total imaging times frequently exceed several minutes, Fig. 6 FD-SOI pFET degradation during continuous SEM imaging at 100 eV and 200 eV. In comparison, the semi-blind probing using the SMARPROBE allows probing of a complete 6T SRAM cell in less than two seconds of accumulated imaging time.

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