edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 30 central feature at ISTFA. It will appear within the ISTFA User Group (UG) sessions, where attendees will engage in interactive conversations on the roadmap survey results from FI-FA tool vendors. These discussions will play a crucial role in shaping actionable plans for the industry. User Groups remain foundational for ISTFA, serving as a dynamic forum for exchanging best practices, tackling current challenges, and shaping the future of failure. At the same time, groundbreaking architectures—such as backside power delivery networks (BSPDN), gate-allaround (GAA) transistors, 3D integrated circuits (3DIC), chiplets, and heterogeneous integration (HI)—are pushing the limits of existing failure analysis methodologies. Additionally, the rise of photonics and advanced materials is introducing new demands for inspection and reliability validation, further reinforcing the need for continuous innovation in analytical techniques and instrumentation. As failure analysis grows increasingly complex, ISTFA User Groups will play a pivotal role in fostering collaboration and driving the breakthroughs necessary to meet these challenges head-on. The ISTFA Expo is a cornerstone of the symposium, offering a premier showcase of novel tools and techniques essential to the failure analysis field. With over 58 exhibitors confirmed and more than 71 booths, the 2025 Expo promises to be a hub of innovation and industry engagement. Beyond exploring exhibitor booths and browsing the latest posters, attendees can take advantage of refreshments in the Expo area, creating the perfect setting to reconnect with colleagues, forge new business relationships, and expand professional networks. For companies, the Expo presents a valuable opportunity to strengthen industry presence, engage with key stakeholders, and connect with both current and potential customers. Exhibitors can highlight the latest products, services, and trends, helping the failure analysis community become efficient and cost-effective in an era of rapid technological advancement. ISTFA also fosters greater participation from academia and students by featuring both a poster contest and a video contest, encouraging engagement from local ISTFA 2025 TECHNICAL SESSIONS Symposium sessions will be packed with high quality, innovative, and original unpublished pre- sentations: • AI Applications for FA • Board and System Level FA • Device Analysis: Case Studies • Die Level Fault Isolation • Emerging FA Techniques • FA Process: Fault Isolation, Mechanisms, & Solutions • Focused Ion Beam (FIB) Circuit Analysis & Edit • FIB Sample Prep • Hardware Security and Counterfeiting • Microscopy and Materials Characterization • More than Moore: Photonics, Magnetics, Magneto-Optics • Nanoprobing and Electrical Characterization • Package Level Fault Isolation • Power Devices (Si, SiC, GaN) • Product Yield, Test, and Diagnostics • Sample Preparation and Device Deprocessing • Scanning Probe Analysis • System In Package and 3D Devices universities. These competitions provide a platform for presenting innovative research topics and exciting results, offering fresh perspectives on failure analysis from emerging researchers. As we embark on the next 50 years of innovation and discovery in failure analysis, join us in celebrating the 51st anniversary of ISTFA milestone for the microelectronics failure analysis community. This is more than just a conference; it is an opportunity to share your expertise, shape the future of the industry, and take your career to new heights. I cannot wait to welcome you to Pasadena this November and experience this journey together. See you there!
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