edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 cell boundaries, both at the direct and recursively nested levels. This enables boundary highlighting or region-ofinterest (ROI) propagation across the system hierarchy. Annotations and structural outlines are reconstructed for the target domain in a new layout layer that can be immediately loaded and modified. Once mapped, the receiving component fully owns the annotations in its native space. This workflow ensures high-fidelity annotation transfer, preserving design context and enabling accurate crossteam communication. For collaborative FA environments spanning design, test, and analysis teams, this capability eliminates misalignment risks and reduces turnaround time by preventing annotation drift between teams working on different levels of the SIP hierarchy. SUMMARY Collectively, these custom CAD tools provide a holistic framework for debug in advanced SIP environments. Through synchronized system launching, dynamic cross-database overlays, and reliable annotation sharing, the applications empower engineers to operate confidently across fragmented design domains. These solutions support yield learning, root cause localization, and efficient failure isolation, which are key enablers for scalable debug workflows in next-generation semiconductor systems. SELECTED REFERENCES 1. Heterogeneous Integration Roadmap, IEEE HIR, 2024, eps.ieee.org/ technology/heterogeneous-integration-roadmap/2024-edition.html. 2. A. Bhattacherjee, et al.: “Heterogeneous Industry Collaboration and System Navigation for Advanced Package Failure Analysis,” ISTFA 2021 Proceedings, 2021, p. 108–114, doi.org/10.31399/asm. cp.istfa2021p0108. 3. S. Sinha, et al.: “A High-density Logic-on-logic 3DIC Design using Face-to-face Hybrid Wafer-bonding on 12 nm FinFET Process,” IEEE IEDM, 2020, p. 15.1.1–15.1.4. 4. S. Naffziger: “Future of AI Hardware Enabled by Advanced Packaging,” AMD. 5. A. Meixner: “Sharing Secure Chip Data for Analytics,” Semiconductor Engineering, April 6, 2021. ABOUT THE AUTHORS Arpan Bhattacherjee is a principal software engineer at Nvidia specializing in silicon failure analysis applications and cross functional workflows, focused on forging tighter links between design and manufacturing to accelerate yield ramps on emerging process technologies. Leveraging deep experience that spans his EDA background, diagnostic fault isolation, and advanced CAD methodologies, he champions creative, data driven approaches that streamline root cause localization and enable faster, more reliable product maturation. An active voice in the failure analysis community, he regularly shares best practices and thought leadership aimed at advancing collaboration across the semiconductor value chain. Arshdeep Singh is a staff applications engineer at Synopsys, where he supports the Avalon failure analysis software and helps customers link design data with physical test results to accelerate root cause localization. He previously worked in physical design engineering at Intel, gaining hands on experience with advanced node place and route and timing closure challenges. Singh holds a bachelor’s degree in electronics and communication engineering and leverages his combined design and FA background to guide semiconductor teams in shortening debug cycles and improving product yield.
RkJQdWJsaXNoZXIy MTYyMzk3NQ==