edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 10 CUSTOM COMPUTER-AIDED DESIGN METHODOLOGIES FOR CROSS-DOMAIN FAILURE ANALYSIS IN ADVANCED SYSTEM-IN-PACKAGE ARCHITECTURES Arpan Bhattacherjee1 and Arshdeep Singh2 1Nvidia Corp., Santa Clara, California 2Synopsys Inc., Sunnyvale, California EDFAAO (2025) 3:10-13 1537-0755/$19.00 ©ASM International® INTRODUCTION The emergence of AI-centric workloads and datacenter-scale systems is fundamentally reshaping the landscape of semiconductor packaging. To meet demands for modularity, bandwidth, and energy efficiency, the indus- try is transitioning from traditional monolithic system-onchip (SOC) designs to heterogeneous integration strategies. These include disaggregated compute, memory, and optical domains assembled into tightly coupled multi-die system-in-package (SIP) architectures. These SIP architectures often feature chiplets, multi-chip modules (MCMs), and 2.5D/3D stacking, and increasingly incorporate silicon photonics for co-packaged optics and universal chiplet interconnect express (UCIe)-based die-to-die connectivity. The architecture in Fig. 1 showcases the trajectory of future SIP design—combining heterogeneous accelerators, 3D front-end integration, optical links, and advanced packaging within a modular substrate. While these innovations deliver exceptional system performance and integration density, they also complicate failure analysis (FA). Debugging across diverse design environments and computer-aided design (CAD) databases is hindered by inconsistent data formats, fragmented coordinate systems, and limited access due to IP protections. These barriers obstruct signal traceability and cross-domain correlation, both of which are essential for yield optimization and fault localization. This article presents custom CAD methodologies designed to support efficient failure analysis across disaggregated domains in advanced heterogeneous packages. By enabling synchronized navigation, cross-domain correlation, and real-time visualization across multiple databases, these tools help overcome IP silos and format fragmentation. The result is a significant improvement in traceability, diagnostic precision, and overall FA throughput—driving higher yield and reliability in next-generation semiconductor systems. CUSTOM CROSS-DOMAIN CAD METHODOLOGIES SYSTEM INVOCATION AND CONTROL Modern multi-die SIP architectures present challenges in managing a unified, coherent debug context, especially when navigating across disparate design domains involving a variety of source data formats (e.g., LEF/DEF, SPICE, GDS/OASIS, Gerber, ODB++, SiP, MCM, BRD, and more). The “Invoke System” application addresses this by enabling synchronized launching and visualization of Fig. 1 Future SIP architecture: Modularity, compute density, and heterogeneous integration consisting of (a) high-speed standardized die-to-die interfaces (UCle), (b) 3D components enabled by front-end precision, (c) heterogeneous compute (accelerators, novel memories), (d) co-packaged optics, (e) memory, and (f) advanced 3.5D packaging. (a) (b) (c) (d) (e) (f)
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