A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2025 | VOLUME 27 | ISSUE 3 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org ELECTRICAL RESISTIVITY AND RESIDUAL STRESS IN SPUTTERED ITO FILMS CHARACTERIZATION OF YIELD-KILLING DEFECTS IN MICRO-LED WAFERS SYSTEMATICALLY DEFOCUSING THE ION BEAM FOR FIB WORKFLOWS CAD METHODS FOR CROSS-DOMAIN FA IN ADVANCED SIP ARCHITECTURES 4 16 10 20
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2025 | VOLUME 27 | ISSUE 3 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org ELECTRICAL RESISTIVITY AND RESIDUAL STRESS IN SPUTTERED ITO FILMS CHARACTERIZATION OF YIELD-KILLING DEFECTS IN MICRO-LED WAFERS SYSTEMATICALLY DEFOCUSING THE ION BEAM FOR FIB WORKFLOWS CAD METHODS FOR CROSS-DOMAIN FA IN ADVANCED SIP ARCHITECTURES 4 16 10 20
edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 ABOUT THE COVER “Vesuvius and Pompeii.” STEM darkfield image of highresistance contact. Photo by Wentao Qin, Brian Anderson, Randy Yach, and Denise Barrientos, Microchip Technology Inc., First Place Winner in False Color Images, 2024 EDFAS Photo Contest. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2025 | VOLUME 27 | ISSUE 3 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Custom CAD Methodologies for Cross-Domain Failure Analysis in Advanced SIP Architectures Arpan Bhattacherjee and Arshdeep Singh By enabling synchronized navigation, cross-domain correlation, and real-time visualization across multiple databases, CAD tools help overcome IP silos and format fragmentation. Author Guidelines Author guidelines and a sample article are available at edfas.org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 10 2 GUEST EDITORIAL Marla L. Dowell 28 SPECIAL ISTFA 2025 PREVIEW Renee Parente 31 ISTFA EXHIBITORS LIST 32 2025 PHOTO CONTEST 33 2025 VIDEO CONTEST 34 HARRIS 2025 SUMMARY Michael DiBattista 36 DIRECTORY OF FA PROVIDERS Rosalinda Ring 38 EDUCATION NEWS Navid Asadi 40 LITERATURE REVIEW Michael R. Bruce 42 PRODUCT NEWS Ted Kolasa 44 INVENTORS CORNER Valerie Brogden 46 TRAINING CALENDAR Rosalinda Ring 48 ADVERTISERS INDEX Spectroscopic Characterization and Detection of Yield-Killing Defects in Micro-LED Wafers Praveena Manimunda This article describes the utility of multimodal spectroscopic metrology tools in characterizing μLED epi-wafers and identifying yield-killing microscopic defects. 16 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Electrical Resistivity and Residual Stress in Sputtered Indium Tin Oxide Thin Films Jianhui Liang, Jiali Zhang, Kurt Johanns, Oskar Amster, Blaise Cuénod, and Rémy Juttin Understanding and controlling the electric resistivity and residual stress of ITO films is crucial for ensuring the performance and reliability of devices using these films. 4 20 16 The Advantages of Systematically Defocusing the Ion Beam for Focused Ion Beam Workflows William M. Mook and Dustin D. Ellis Purposefully defocusing the ion beam for standard FIB processing leads to increased efficiency, reduced curtaining, and decreased thermal damage. 20 10
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 2 AUGUST 2025 | VOLUME 27 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL FROM CLASSROOM TO CLEANROOM: EDGE AND THE POWER OF INDUSTRY-ACADEMIC COLLABORATION Marla L. Dowell, EDGE Consortium marla.l.dowell@dartmouth.edu edfas.org (continued on page 35) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2025 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Dowell In the rapidly evolving field of failure analysis, the need for skilled professionals who can quickly transition from academic settings to productive industry roles has never been greater. As technology advances and devices become more complex, the demand for experts who can diagnose and address device failures is on the rise. Failure analysis, by its nature, is an interdisciplinary field drawing talent from a wide variety of science, technology, engineering, and mathematics (STEM) disciplines. This presents a unique opportunity for academia and industry to collaborate in training early career professionals, ensuring they are well-equipped to tackle the challenges of failure analysis. One of the key initiatives facilitating this partnership is the Expanding Dynamic Growth in Engineering (EDGE) Consortium. Led by Dartmouth and Indiana University, EDGE is dedicated to bridging the gap between the fundamental knowledge that students acquire in college and the practical, contextual environment of industry applications. By focusing on disciplinary literacy, EDGE aims to break down barriers and accelerate the transition for students entering the semiconductor workforce. Disciplinary literacy involves understanding the specific language, practices, and methodologies of a particular field. In the context of failure analysis, this means not only having a strong foundation in the principles of electronics and materials science but also being able to apply this knowledge to real-world scenarios. This is where the collaboration between academia and industry is crucial. Academia provides the theoretical foundation students need through rigorous coursework, fostering a deep understanding of electronic device operation and failure mechanisms. Yet, this knowledge alone is not enough. Students must also learn to apply these principles in practical settings, where real-world variables differ significantly from those in the classroom. To meet the ambitious goal of educating more than 100,000 workers by 2030,[1] we must broaden access to include STEM students beyond traditional engineering, such as computer scientists, physicists, chemists, and mathematicians, and develop ways to translate their diverse learning paths into failure analysis competencies. The industry complements this by providing a contextual environment where theory meets application. Through internships, co-ops, and collaborative projects, industry partners provide hands-on experiences that expose students to real-world challenges and solutions, effectively bridging the gap between academic preparation and professional practice. EDGE plays a pivotal role in facilitating these partnerships. Through the EDGE Scholars program, the consortium has registered 475 students over
NOVEMBER 16–20, 2025 PASADENA CONVENTION CENTER | PASADENA, CA SCALING BEYOND MOORE’S LAW: HETEROGENEOUS COMPUTING AND ADVANCED PACKAGING SAVE THE DATE! High-performance compute solutions are simultaneously driving innovations in advanced packaging, high bandwidth I/O, heterogeneous compute architectures, device architectures, silicon scaling, and more. Each of these advances pose a unique challenge to failure analysis, but together present a disruption that the failure analysis community has yet to experience. Now is the time to act! New analysis methods and instrumentation must be developed to address these challenges and deliver the stellar analysis capability our failure analysis community is known for. Industry collaboration is the key to success. Together, we will spearhead the breakthrough approaches necessary to overcome the complex disruptions our society is facing as high-performance compute solutions scale beyond Moore’s law. STUDENT POSTER SESSION The 51st International Symposium for Testing and Failure Analysis (ISTFA) invites community college, undergraduate, and graduate students to participate in this year’s student poster contest. This program is designed to: • Foster exchanges between academia and the failure analysis engineering community. • Provide students with an opportunity to gain exposure to failure analysis within the microelectronics sector and to network with professionals and peers in the field. ISTFA is the premier microelectronics/semiconductor failure analysis conference in North America. It will be held at the Pasadena Convention Center from November 16–20, 2025. Learn more at ISTFAevent.org. • Access to tutorials • Four days of technical programming • Keynotes & Panel Discussion • Entrance to the Exhibit Hall Complete Full Conference Ticket Includes: Student Registration Available • Welcome Reception with the Exhibitors • Refreshment Breaks each day • Lunch vouchers • One ticket to the Social Event REGISTRATION OPENS IN JULY!
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 4 EDFAAO (2025) 3:4-9 1537-0755/$19.00 ©ASM International® ELECTRICAL RESISTIVITY AND RESIDUAL STRESS IN SPUTTERED INDIUM TIN OXIDE THIN FILMS Jianhui Liang1, Jiali Zhang1, Kurt Johanns1, Oskar Amster1, Blaise Cuénod2, and Rémy Juttin2 1KLA Corp., Milpitas, California 2Center of MicroNanoTechnology, EPFL, Lausanne, Switzerland jianhui.liang@kla.com INTRODUCTION Transparent conductive thin films are crucial in various semiconductor devices, including solar cells, liquid crystal displays, light-emitting diodes, and sensors. Indium tin oxide (ITO) is a popular choice for these applications due to its excellent electrical conductivity, optical clarity, and unique nonlinear properties. Various methods can be used to create ITO thin films, such as magnetron sputtering, thermal evaporation, plasma ion-assisted deposition, and activated reactive evaporation. Among these, sputtering is particularly favored by industry for producing films with a dense structure and high transparency. The electrical resistivity in ITO determines its efficiency as a conductor, directly impacting the performance of devices in which it is integrated. A material with suboptimal resistivity may cause excessive heat dissipation and degrade the overall reliability of the device, leading to inefficiencies or failures in electronic and photonic applications. As such, understanding the factors that influence ITO’s resistivity, such as film thickness, grain size, composition, and deposition techniques, ensures that the material can be tailored for specific applications, providing the optimal balance between electrical conductivity and optical transparency. On the other hand, the residual stress that arises from the ITO film growth process can significantly impact performance of the ITO devices. One major issue is stress-induced warpage, which can disrupt the flatness of devices and complicate subsequent production steps. For example, tensile stress might lead to cracking or delamination, while compressive stress could cause buckling or warping. These mechanical failures can translate into electrical issues, such as open or short circuits, which are critical in precision applications like displays and sensors. Understanding and controlling residual stress is therefore essential to prevent mechanical failures and improve the longevity of devices, particularly in flexible electronics or applications subjected to thermal or mechanical stress. This article describes a study on the electrical resistivity and residual stress in sputtered indium tin oxide (ITO) films. The electrical resistivity of the ITO films was determined by measuring their thickness and sheet resistance, while the residual stress was quantified using a stylus profiler. It was observed that electric resistivity varies spatially and changes with film thickness. These variations are influenced by growth conditions, as well as electron scattering from surfaces and grain boundaries. Additionally noted was a transition from tensile to compressive stress as the film thickness increased, closely linked to the grain evolution process. Understanding these phenomena is crucial for enhancing the performance and reliability of electronic devices. By addressing the mechanical and electrical impacts of stress in ITO films, more robust and durable semiconductor devices can be developed, thereby reducing the risk of device failure. SAMPLE GROWTH ITO films are typically deposited on transparent insulating substrates that are in turn used for various electronic devices. In this study, ITO films were deposited on 100 mm diameter Borofloat 33 wafers, sourced from Siegert Wafer, using a standard radio frequency (RF) sputtering technique on a Pfeiffer Spider 600 system. The planar ITO target used for deposition measured 200 mm. The deposition process was carried out at room temperature with a target power of 500 W. The argon gas flow was maintained at 15 standard cubic centimeters per minute (cc/min), and the chamber discharge pressure was kept at approximately 0.5 Pa. Nine ITO films of varying thicknesses were prepared under
edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 identical growth conditions, achieving a growth rate of 1.43 nm/s. These consistent growth conditions ensured uniform stress evolution across the samples. SURFACE METROLOGY TECHNIQUES The resistivity of a conductive film can be calculated using the equation: (Eq 1) where ρ is the resistivity, RS is the sheet resistance, and tf is film thickness. The residual stress in the thin-film layer can be calculated using the Stoney equation:[1] (Eq 2) where σ is the stress, κ is the change of curvature, E/(1-ν) is the biaxial elastic modulus of the substrate (E represents Young’s modulus of the substrate, and ν represents the Poisson’s ratio), ts is substrate thickness, tf is film thickness. Figure 1 shows the surface metrology techniques used in the electrical resistivity and residual stress measurement. To evaluate the residual stress and resistivity of ITO films deposited on a glass substrate, it is necessary to measure the sheet resistance, film thickness, elastic modulus, and wafer curvature. These parameters can be measured using a four-point probe (4PP), a reflectometer, a nanoindenter, and a stylus profiler, respectively. The sheet resistance of the ITO films was determined using a four-point-probe system, specifically the Filmetrics R50 from KLA Instruments, equipped with a 4PP Type B probe featuring a 0.1 mm tip radius and 1.0 mm tip spacing. The thickness of the ITO films was measured using a Filmetrics F50-UVX reflectometer from KLA Instruments, which utilizes a light source covering wavelengths from 190 to 1700 nm. This setup enables thickness measurements ranging from 5 nm to 250 µm with an accuracy of ± 1 nm. The change in wafer curvature due to ITO film deposition can be measured using a stylus profiler both before and after the deposition process. For this measurement, the HRP-260 automated stylus profiler from KLA Instruments was used. The scan length was set to 80 mm, which is 80% of the wafer’s diameter. After each scan, the system rotates the sample by 15° and performs another scan. This process is repeated to create a 3D wafer curvature map with 12 traces for each sample. The change in curvature is determined by comparing the measurements taken before and after the ITO film deposition. The elastic modulus of ITO films was measured using a G200X Nanoindenter from KLA Instruments, equipped with a wafer chuck and a diamond Berkovich indenter tip. A standard method was used to correct for the influence of the substrate on the measurement. Arrays of at least 20 indentations were made at the center of the wafer, and the results were reported for 25% of the film thickness. A reference wafer made of fused silica, with a known modulus of 73.0 GPa and a Poisson’s ratio of 0.16, was used to calibrate the indenter tip. This reference wafer was measured to have an elastic modulus of 72.9 ± 0.4 GPa using the same method as for the ITO films. The elastic moduli of ITO films with thicknesses of 45, 91, 451, and 559 nm were evaluated in the experiment. In addition, atomic force microscopy (AFM) was used to perform grain analysis on the ITO films. Studies have shown that grain size measurements from surface techniques such as AFM are consistent with transmission measurements for the ITO material.[2] Fig. 1 Surface metrology techniques used in electrical resistivity and residual stress measurement.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 6 ELECTRICAL RESISTIVITY OF ITO Figure 2a illustrates the thickness map of the thickest ITO film, measured using a 115-point map across the entire 100 mm diameter wafer with a 5 mm edge exclusion. The center thickness is 615 nm, while the edge thickness is 510 nm. The thickness gradually decreases from the center to the edge, forming a circular distribution. Figure 2b shows the sheet resistance map of the same wafer. It reveals that both the center and the edge exhibit high sheet resistance, approximately 4.6 Ω/sq, while the area in between has the lowest sheet resistance, around 3.3 Ω/sq. According to Eq 1, if the ITO film has uniform resistivity across the wafer, RS should be inversely proportional to the film thickness. However, no monotonic change in RS is observed from the center to the edge, as seen with the film thickness. This discrepancy between the ITO thickness map and the RS map suggests a variation in ITO resistivity from the wafer center to the edge. Figures 2c and 2d depict the ITO thickness map and sheet resistance map from a different sample. The ITO thickness ranges from 75 to 89 nm, decreasing from the center to the edge. The sheet resistance at the wafer edge is high, at 116 Ω/sq, while it decreases to 25 Ω/sq toward the center. The center of the wafer shows an RS of approximately 50 Ω/sq. To better understand the spatial distribution of the ITO thickness dITO and the sheet resistance RS, and to calculate the point-to-point resistivity ρ, line scans of dITO and RS across the wafer were conducted for all nine ITO samples. The line scan was performed from X = –45 mm to X = 45 mm at 1 mm intervals. Figure 3a shows the line scan of the ITO thickness for all nine samples. The ITO thickness at the wafer center ranges from 15 to 615 nm, with all samples exhibiting a gradual decrease in thickness from the center to the edge. Figure 3b presents the line scan of the ITO sheet resistance for all nine samples. For thin ITO films, the RS at the center is generally lower than at the edge. However, for thicker ITO films, the sheet resistance does not show a monotonic change from Fig. 2 (a) Thickness map and (b) sheet resistance map of ITO film with thickness of 615 nm in the center. (c) Thickness map and (d) sheet resistance map of ITO film with thickness of 89 nm in the center. The samples are ITO films deposited on 100 mm glass wafers. Fig. 3 (a) Thickness line profiles and (b) sheet resistance line profiles of ITO films with thickness ranging from 15 to 615 nm in the center. (c) Resistivity line profiles of ITO films calculated from the thickness and sheet resistance results. (d) Schematic cross-section of a circular magnetron sputtering head. (a) (b) (c) (d) (a) (b) (c) (d)
edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 the wafer center to the edge. Applying Eq 1 to the data from Figs. 3a and b, created the resistivity map of the ITO films, as shown in Fig. 3c. For thick ITO films with a thickness dITO of 89 nm or greater, the lowest resistivity values are approximately 2 x 10-4 Ω·cm, which is close to the bulk resistivity of the ITO film. For thin ITO films with a thickness dITO of 50 nm or less, the resistivity values range between 5 x 10-4 Ω·cm to 1.25 x 10-3 Ω·cm. This data illustrates the spatial distribution of resistivity ρ for all the ITO samples. Figure 3d depicts a schematic cross-section of a circular magnetron sputtering head. This configuration includes permanent magnets positioned behind the target, generating a high-density, torus-shaped plasma, with the substrate placed parallel to the target. The magnetic field increases the probability of electron collisions with neutral gas atoms, significantly boosting plasma density and, consequently, the sputtering rate. This setup results in a distinct erosion track on the target surface, adjacent to the high-density plasma torus. Studies have shown that when depositing metal oxide films using RF sputtering, the high flux of positive ions impacting the target at the erosion track releases lowenergy secondary electrons. These electrons can easily attach to oxygen atoms, forming negative oxygen ions, which are then accelerated toward the substrate by the cathode sheath. This indicates that the spatial distribution of resistivity in relation to the erosion track on the target surface is influenced by energetic negative oxygen ions. The findings suggest that the primary factor affecting the resistivity and band gap energy profiles of the deposited films is the depletion of metal due to re-sputtering by these energetic negative oxygen ions.[3,4] For these RF-sputtered ITO films, the resistivity shows significant spatial distribution, which is consistent with other studies on metal oxide films such as aluminumdoped zinc oxide.[3,4] The results suggest that the resistivity distribution is highly impacted by the growth conditions. Therefore, the uniformity of electronic properties needs to be monitored during the film deposition process. RESIDUAL STRESS OF ITO Figures 4a and b depict two distinct bow shapes observed from ITO films with average thickness of 14 and 559 nm. For the 14 nm ITO film, the wafer center appears lower than the edges, while the opposite trend is observed for the 559 nm ITO film. Figures 4c and d are the stress map calculated from Figs. 4a and b using Eq 2. The stress versus ITO thickness is plotted in Fig. 4e. The thinnest (14 nm) ITO film sample exhibits a tensile stress of 1.90 GPa. As the ITO film thickness increases, the tensile stress decreases and eventually transitions to compressive stress, stabilizing at approximately -0.4 GPa. The stress error was indicated with an error bar, which was carefully estimated considering the film thickness measurement error as well as the curvature measurement error. In the early stages of ITO film growth, crystals nucleate with different orientations, forming equiaxed grains Fig. 4 (a) 3D bow of ITO (d = 14 nm)/glass; (b) 3D bow of ITO (d = 559 nm)/glass; (c) 3D stress of ITO (d = 14 nm)/glass; (d) 3D stress of ITO (d = 559 nm)/glass; and (e) ITO film stress versus film thickness.[5] (a) (b) (c) (d) (e)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 8 that grow and create grain boundaries. This process induces tensile stress as grains attract each other. Nix and Clemens’ model estimates this stress based on surface and grain boundary energies, showing it is proportional to the root of the reciprocal of grain size: (Eq 3) where σT is the tensile stress, Y is Young’s modulus, ν is the Poisson’s ratio, d is the grain size, and γs and γgb are the surface and grain boundary energies of the film, respectively. This model indicates that the tensile stress is proportional to the root of the reciprocal of the grain size. Experimental data in Fig. 5 aligns with this model. Elastic modulus measurements for ITO films indicate consistent crystal structure and composition across thicknesses. For a 45 nm ITO film, the surface and grain boundary energy difference is calculated to be 6.4 ± 1.3 J/m². During columnar grain growth, compressive stress dominates, stabilizing at -0.4 GPa. The steady-state residual compressive stress was also observed in high-mobility materials like Cu and Ag, which is closely tied to the material and growth conditions.[6,7] SUMMARY The study investigated electrical resistivity, thickness, and residual stress of RF-sputtered ITO films. Nine films of varying thicknesses were prepared under identical conditions. The electrical resistivity results revealed a significant spatial distribution of resistivity, which was influenced by the growth conditions of the films. This variation is attributed to energetic negative oxygen ions formed during RF sputtering, which cause metal depletion through re-sputtering. The findings emphasize the importance of monitoring the uniformity of electronic properties during the film deposition process. It was concluded that assessing thickness or sheet resistance alone is insufficient for effective ITO film process control. Instead, both factors must be combined to accurately calculate resistivity. This comprehensive approach provides a better understanding of the uniformity of electrical properties, offering valuable insights into improving the deposition process. On the other hand, the residual stress result suggests that ITO films exhibit a transition of stress from tensile to compressive as the thickness of ITO films is increased. The tensile stress originated from the impingement and coalescence of newly deposited equiaxed grains, while the observed compressive stress was attributed to the incorporation of excess material in the boundaries of columnar grains. The ability to monitor electric resistivity distribution and stress evolution in sputtered ITO films on glass substrates provides valuable insights for process control in ITO device manufacturing. Understanding and controlling the electric resistivity and residual stress of ITO films are crucial for ensuring the performance and reliability of devices utilizing these films. REFERENCES 1. G.G. Stoney: “The Tension of Metallic Films Deposited by Electrolysis,” Proc. R. Soc. London, 1909, 82, p. 172. 2. N.M. Ahmed, et al.: “The Effect of Post Annealing Temperature on Grain Size of Indium-Tin-Oxide for Optical and Electrical Properties Improvement,” Results Phys. 2019, 13, p. 102159. 3. K. Norrman, P. Norby, and E. Stamate: “Preferential Zinc Sputtering during the Growth of Aluminum Doped Zinc Oxide Thin Films by Radio Frequency Magnetron Sputtering,” J. Mater. Chem. C, 2022, 10, p. 14444. 4. S. Khan and E. Stamate: “Comparative Study of Aluminum-Doped Zinc Oxide, Gallium-Doped Zinc Oxide and Indium-Doped Tin Oxide Thin Films Deposited by Radio Frequency Magnetron Sputtering,” Nanomaterials, 2022, 12, p. 1539. 5. J. Liang, et al.: “Quantitative Study of the Thickness-dependent Stress in Indium Tin Oxide Thin Films,” Thin Solid Films, 2024, 788, p. 140163. 6. E. Chason, et al.: “Origin of Compressive Residual Stress in Polycrystalline Thin Films,” Phys. Rev. Lett., 2022, 88, p. 156103. 7. F. Spaepen: “Interfaces and Stresses in Thin Film,” Acta Mater., 2000, 48, p. 31. Fig. 5 Stress as a function of the root of the reciprocal of the grain size. The red dashed line indicates the fitting line using Nix’s theoretic model. The inserted graph shows the elastic modulus values of the ITO films measured with nanoindentation.[5] ITO films have been observed by stylus profilometry to exhibit a transition of stress from tensile to compressive as the thickness of ITO films is increased. This analysis provides valuable insights into the evolution of stress versus thickness of ITO films and can serve as a reference for monitoring and modulating the stress during the production process control of ITO devices.
edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 ABOUT THE AUTHORS Jianhui Liang is an applications engineering manager at KLA, where he leads the applications development team within KLA Instruments. Liang received his B.S. and Ph.D. in physics from Fudan University in 2011 and 2016, respectively. He has authored over 25 publications, which have garnered more than 600 citations. His work has been published in peer-reviewed journals such as Applied Physics Letters, Optics Express, Advanced Optical Materials, and Physical Review B. Jiali Zhang is a product development engineer at KLA. She is responsible for the development of advanced metrology products, including optical profilers, thin film reflectometers, sheet resistance measurement tools, and stylus profilers. She earned her Ph.D. in analytical chemistry from the University of California, Davis, where she developed SPM-based nanoprinting methodology for 3D nanofabrication. Her work has been published in journals such as the Journal of Physical Chemistry, JPC Letters, Tetrahedron Letters, Stem Cells, and Thin Solid Films. Kurt Johanns is an applications scientist at KLA. Based in Oak Ridge, Tenn., he primarily works with the Nanoindentation team in the KLA Instruments division. He received his Ph.D. in materials science and engineering from the University of Tennessee in 2014 and has been in the small-scale mechanical testing community for 20 years. Johanns enjoys developing unique test experiments for promoting and characterizing the failure of materials and material systems. Oskar Amster is the director of marketing at KLA Instruments, a division of KLA Corp. Amster has been with KLA in various roles for 12 years and worked for a range of instrumentation companies as an applications engineer, product/sales manager, and progressed to various management roles in the materials characterization field. He has been in the surface metrology and materials characterization field for over 25 years. Amster holds a master of science in materials engineering and a bachelor of science in physics from California Polytechnic San Luis Obispo. Blaise Cuénod is a process engineer at the Center of MicroNanoTechnology (CMi) at EPFL where he is in charge of the PVD and PECVD processes development for the CMi users community. Prior to joining CMi in 2021, he graduated from EPFL after completing a master’s in materials science and engineering with a minor in energy. Rémy Juttin studied at the University of Orléans and holds an engineering degree in electronics and optics, as well as a master’s degree in environments and materials in extreme conditions. He joined the Center of MicroNanoTechnology (CMi) at EPFL in 2015 as process engineer. Initially involved in the wet and dry etching section, he has been responsible for PVD equipment at CMi for over five years. Visit the Electronic Device Failure Analysis Society website edfas.org
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 10 CUSTOM COMPUTER-AIDED DESIGN METHODOLOGIES FOR CROSS-DOMAIN FAILURE ANALYSIS IN ADVANCED SYSTEM-IN-PACKAGE ARCHITECTURES Arpan Bhattacherjee1 and Arshdeep Singh2 1Nvidia Corp., Santa Clara, California 2Synopsys Inc., Sunnyvale, California EDFAAO (2025) 3:10-13 1537-0755/$19.00 ©ASM International® INTRODUCTION The emergence of AI-centric workloads and datacenter-scale systems is fundamentally reshaping the landscape of semiconductor packaging. To meet demands for modularity, bandwidth, and energy efficiency, the indus- try is transitioning from traditional monolithic system-onchip (SOC) designs to heterogeneous integration strategies. These include disaggregated compute, memory, and optical domains assembled into tightly coupled multi-die system-in-package (SIP) architectures. These SIP architectures often feature chiplets, multi-chip modules (MCMs), and 2.5D/3D stacking, and increasingly incorporate silicon photonics for co-packaged optics and universal chiplet interconnect express (UCIe)-based die-to-die connectivity. The architecture in Fig. 1 showcases the trajectory of future SIP design—combining heterogeneous accelerators, 3D front-end integration, optical links, and advanced packaging within a modular substrate. While these innovations deliver exceptional system performance and integration density, they also complicate failure analysis (FA). Debugging across diverse design environments and computer-aided design (CAD) databases is hindered by inconsistent data formats, fragmented coordinate systems, and limited access due to IP protections. These barriers obstruct signal traceability and cross-domain correlation, both of which are essential for yield optimization and fault localization. This article presents custom CAD methodologies designed to support efficient failure analysis across disaggregated domains in advanced heterogeneous packages. By enabling synchronized navigation, cross-domain correlation, and real-time visualization across multiple databases, these tools help overcome IP silos and format fragmentation. The result is a significant improvement in traceability, diagnostic precision, and overall FA throughput—driving higher yield and reliability in next-generation semiconductor systems. CUSTOM CROSS-DOMAIN CAD METHODOLOGIES SYSTEM INVOCATION AND CONTROL Modern multi-die SIP architectures present challenges in managing a unified, coherent debug context, especially when navigating across disparate design domains involving a variety of source data formats (e.g., LEF/DEF, SPICE, GDS/OASIS, Gerber, ODB++, SiP, MCM, BRD, and more). The “Invoke System” application addresses this by enabling synchronized launching and visualization of Fig. 1 Future SIP architecture: Modularity, compute density, and heterogeneous integration consisting of (a) high-speed standardized die-to-die interfaces (UCle), (b) 3D components enabled by front-end precision, (c) heterogeneous compute (accelerators, novel memories), (d) co-packaged optics, (e) memory, and (f) advanced 3.5D packaging. (a) (b) (c) (d) (e) (f)
edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 all components defined in a SIP layout through a single user interface. The Invoke System functionality is initiated by a system configuration file that defines the spatial hierarchy and alignment relationships among components within a heterogeneous SIP (Fig. 2). This configuration file is not merely a generic listing; it specifies critical transformation parameters—including translation, rotation, mirroring, and scaling—that govern how each child component is positioned relative to its parent. By encoding these spatial relationships, the configuration file enables consistent navigation and synchronized visualization across multiple databases, establishing a unified framework for correlated debug and cross-domain failure analysis. Each component’s relation is encoded using matrix transformations that allow the CAD tools to synchronize views and transfer annotations precisely. Because the structure supports nested hierarchies, it allows a component to act as a parent to its own children, facilitating scalable recursive coordination across the system. In practice, this configuration file can be manually created or adjusted if alignment data such as component offsets, pad layer positions, or known transformation parameters, are available from design teams or process flows. When this information is unavailable, some commercial CAD environments support semi-automated alignment through geometry-based pad layer matching. These methods rely on overlaying bump or pad structures at the package-die interface to infer transform relationships. By simplifying CAD setup including configuration, permissions, and startup commands, the tool reduces human error and improves efficiency. For failure analysts, it guarantees synchronized, to-scale views across domains which is critical for tasks such as signal tracing across stacked dies or correlating package traces with on-die features. DYNAMIC REAL-TIME COMPONENT OVERLAY To support advanced debugging within multi-layered, stacked-die packages, it is essential to enable visual correlation of sub-components from parent-level views. The second application implements a dynamic, remote procedure protocol (RPC)-based overlay system that aligns child die views directly into the package-level visualization environment. At runtime, the overlay script determines whether it was launched from the parent or child view, then locates the corresponding system configuration file to retrieve the appropriate transformation matrix. If launched from a child view, the script captures the active view’s field-ofinterest and transforms it into the parent layout’s coordinate space. It then commands the parent view to pan and zoom to the relevant area. If launched from a parent view, the script iterates through each child defined in the configuration file, evaluates which are spatially relevant to the current view, and triggers dynamic overlays only for those components. Overlays are generated by remotely capturing the child layout window and rendering the image with a transparent background to only retain polygons. This image is then aligned and loaded into the parent view as a transient visual layer—preserving memory efficiency and avoiding persistent database load. Fig. 2 “Invoke System” application launch pad with system-hierarchy and component relationship awareness.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 12 For system-level failure analysis, especially when investigating packaged devices, dynamic child overlays provide critical visibility into how individual dies or subcomponents are positioned relative to the larger system. This allows analysts to examine clearances, stacking tolerances, and potential interactions between different package elements, ensuring that no unintended mechanical or thermal damage happens during probing, deprocessing, or imaging. It also helps assess whether a defect location aligns with structural obstructions or bonding interfaces, which could otherwise complicate fault isolation. This overlay workflow enables high-precision crossdomain analysis, especially in scenarios where overlapping defects span multiple dies or reside at die-to-package boundaries. The dynamic, on-demand nature of the tool allows analysts to explore complex debug paths with agility, adjusting overlays based on current focus without overwhelming system resources. PERSISTENT ANNOTATION SHARING Annotations including markups, bounding boxes, labels, and probe points are central to collabora- tive failure analysis. However, in SIP systems, transfer- ring such annotations between parent and child CAD environments requires rigorous transformation to main- tain accuracy and context. The third solves this by implementing a complete import/export framework for annotation sharing between heterogeneous com- ponents. Unlike overlays, which are static visual images rendered temporarily on top of a layout for visual alignment, annotations represent live geometric and textual objects that can be manipulated, extended, or deleted within the receiving environment (Fig. 3). They are embedded into the destination layout’s coordinate system, enabling native interaction such as editing, labeling, measurement, or further markup. This persistent and editable nature makes them ideal for ongoing debug, documentation, and collaboration workflows. The tool operates in two modes: exporting annotations from a parent (e.g., package) to all children (e.g., dies), and importing annotations from children to the parent. It begins by capturing the relevant annotation content into a virtual layer file format, then parses each geometric primitive while applying affine transformations defined in the system configuration file. Transformation is applied to all coordinate-sensitive primitives—including boxes, wires, text, and polygons— while accounting for shrink factors, rotation angles, and mirror states. In addition to annotation primitives, virtual layers can be used to transfer full component or Fig. 3 Cross-database annotation sharing between board, substrate, interposer, and dies.
edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 cell boundaries, both at the direct and recursively nested levels. This enables boundary highlighting or region-ofinterest (ROI) propagation across the system hierarchy. Annotations and structural outlines are reconstructed for the target domain in a new layout layer that can be immediately loaded and modified. Once mapped, the receiving component fully owns the annotations in its native space. This workflow ensures high-fidelity annotation transfer, preserving design context and enabling accurate crossteam communication. For collaborative FA environments spanning design, test, and analysis teams, this capability eliminates misalignment risks and reduces turnaround time by preventing annotation drift between teams working on different levels of the SIP hierarchy. SUMMARY Collectively, these custom CAD tools provide a holistic framework for debug in advanced SIP environments. Through synchronized system launching, dynamic cross-database overlays, and reliable annotation sharing, the applications empower engineers to operate confidently across fragmented design domains. These solutions support yield learning, root cause localization, and efficient failure isolation, which are key enablers for scalable debug workflows in next-generation semiconductor systems. SELECTED REFERENCES 1. Heterogeneous Integration Roadmap, IEEE HIR, 2024, eps.ieee.org/ technology/heterogeneous-integration-roadmap/2024-edition.html. 2. A. Bhattacherjee, et al.: “Heterogeneous Industry Collaboration and System Navigation for Advanced Package Failure Analysis,” ISTFA 2021 Proceedings, 2021, p. 108–114, doi.org/10.31399/asm. cp.istfa2021p0108. 3. S. Sinha, et al.: “A High-density Logic-on-logic 3DIC Design using Face-to-face Hybrid Wafer-bonding on 12 nm FinFET Process,” IEEE IEDM, 2020, p. 15.1.1–15.1.4. 4. S. Naffziger: “Future of AI Hardware Enabled by Advanced Packaging,” AMD. 5. A. Meixner: “Sharing Secure Chip Data for Analytics,” Semiconductor Engineering, April 6, 2021. ABOUT THE AUTHORS Arpan Bhattacherjee is a principal software engineer at Nvidia specializing in silicon failure analysis applications and cross functional workflows, focused on forging tighter links between design and manufacturing to accelerate yield ramps on emerging process technologies. Leveraging deep experience that spans his EDA background, diagnostic fault isolation, and advanced CAD methodologies, he champions creative, data driven approaches that streamline root cause localization and enable faster, more reliable product maturation. An active voice in the failure analysis community, he regularly shares best practices and thought leadership aimed at advancing collaboration across the semiconductor value chain. Arshdeep Singh is a staff applications engineer at Synopsys, where he supports the Avalon failure analysis software and helps customers link design data with physical test results to accelerate root cause localization. He previously worked in physical design engineering at Intel, gaining hands on experience with advanced node place and route and timing closure challenges. Singh holds a bachelor’s degree in electronics and communication engineering and leverages his combined design and FA background to guide semiconductor teams in shortening debug cycles and improving product yield.
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 16 SPECTROSCOPIC CHARACTERIZATION AND DETECTION OF YIELD-KILLING DEFECTS IN MICRO-LED WAFERS Praveena Manimunda HORIBA, Irvine, California praveena.manimunda@horiba.com EDFAAO (2025) 3:16-19 1537-0755/$19.00 ©ASM International® INTRODUCTION The burgeoning demand for high-performance displays with enhanced brightness, reduced power consumption, and extended operational lifetimes has positioned micro-LED (µLED) technology as a leading contender to supersede existing organic light-emitting diode (OLED) and liquid crystal display (LCD) technologies.[1] The market for µLED displays is projected to reach USD 21 billion by 2028, driven by applications in automotive panels, smartwatches, mobile devices, and augmented reality (AR) glasses. Achieving the high pixel densities required for wearable and AR applications necessitates the fabrication of µLEDs with dimensions of 3 µm or smaller. However, the transfer of these micron-scale dies to the backplane and the inherent challenges in maintaining high production yields at such small dimensions remain significant hurdles to full commercialization.[2] Low yields directly translate to increased production costs, hindering the widespread adoption of µLED displays. The conventional µLED display manufacturing process (Fig. 1) involves two primary stages: the growth of an epitaxial wafer (epi-wafer) and the subsequent dicing and processing of this wafer to create individual LEDs with contact pads. Imperfections or defects introduced during the epitaxial growth stage critically impact the final performance of the fabricated µLEDs, leading to issues such as uneven color uniformity, reduced brightness, and the presence of nonfunctional (dead) pixels. Early identification and characterization of microscopic defects at the wafer level are therefore paramount for enhancing die yield and reducing manufacturing costs. While macroscopic defects and surface contaminants can often be identified using conventional imaging inspection tools, the detection and analysis of structural defects and epitaxial growth imperfections necessitate the application of advanced spectroscopic techniques. This article describes the utility of HORIBA’s multimodal spectroscopic metrology tools, specifically the LabRAM Odyssey and SMS320 systems, in characterizing µLED epi-wafers and identifying yield-killing microscopic defects through Raman spectroscopy, photoluminescence (PL) mapping, high-resolution PL spectroscopy, and time-resolved photoluminescence (TRPL). METHODS AND MATERIALS This study utilized commercially available 2-inch GaN-based epitaxial wafers emitting blue (~450 nm) and green (~532 nm) light. For defect identification and characterization, full wafer PL mapping was performed using a HORIBA SMS 320 system, integrated with 375 nm excitation source. The spatial resolution of the mapping was optimized to identify regions of nonuniformity. High-resolution PL spectroscopy was conducted on selected defect regions Fig. 1 Schematic illustration of µLED-based display production process.[2]
edfas.org 17 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 identified in the full wafer PL maps using the LabRAM Odyssey system with a spatial resolution down to 200 nm. Emission wavelength shifts within the defect regions were analyzed to understand the nature of the structural imperfections. Time-resolved photoluminescence measurements were performed at both defect and neighboring nondefective regions using a pulsed laser excitation source to investigate the impact of defects on minority carrier lifetimes. The decay curves were analyzed to determine the radiative and nonradiative recombination rates. Raman spectroscopy was employed to analyze the residual stress in the vicinity of specific surface defects, such as micro-pits and micro-cracks. Shifts in the E2 phonon mode of GaN were mapped across these defect regions using the LabRAM Odyssey system. Finally, large-area PL mapping was performed on a commercially available LED display panel using the HORIBA SMS system to identify defective pixels and assess brightness uniformity across the panel. High-resolution PL mapping with a 5 µm step size was subsequently conducted on selected defective and normal pixels to investigate local intensity variations. DATA AND RESULTS FULL WAFER PHOTOLUMINESCENCE MAPPING Full wafer PL intensity maps (Figs. 2a and b) of both blue and green emitting epi-wafers revealed significant nonuniformity across the wafer surface. The green LED wafer exhibited a higher degree of nonuniformity, particularly at the edges, and showed evidence of bowing. Both wafers displayed a noticeable PL emission wavelength shift as measurements progressed from the center toward the edge (Figs. 2e and f), indicating the presence of structural defects or variations in the epitaxial layer composition. Notably, the PL map of the 532 nm (green) µLED wafer (Fig. 2b) showed distinct low-intensity regions, or “cold spots,” suggesting localized defects. HIGH-RESOLUTION PHOTOLUMINESCENCE OF COLD SPOTS Optical microscopy of the cold spot regions revealed clusters of defects on the wafer surface. High-resolution PL mapping (200 nm step size) of these de- fect regions demonstrated a clear shift in the PL emission frequencies compared to the surrounding nondefective areas. This spectral shift indicates the presence of point defects or local strain variations within the epitaxial structure (Fig. 3b). TIME-RESOLVED PHOTOLUMINESCENCE ANALYSIS TRPL spectra acquired at a cold spot defect and a neighboring nondefective region (Fig. 3c) showed a significant reduction in the carrier lifetime at the defect site. This observation suggests that the defects act as nonradiative recombination centers, trapping carriers and reducing the efficiency of radiative emission, ultimately leading to lower PL intensity. Fig. 2 (a) and (b) Full wafer PL maps, showing 450 and 532 nm peak intensity variations. (c) and (d) Variation in emission wavelengths. (e) and (f) PL point spectra extracted from the four points marked on (c) and (d). Both wafers showed a significant shift in the PL emission, indicating structural defects. (a) (b) (c) (d) (e) (f)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 3 18 RAMAN SPECTROSCOPY OF SURFACE DEFECTS Optical microscopy of larger cold spots revealed structures consistent with micro-pits, often surrounded by Fig. 3 Effect of yield-killing structural defects on emission wavelength and carrier dynamics. (a) Optical image of the defect region. (b) High-resolution PL map (200 nm, step size) showing changes in the emission wavelength. (c) TRPL spectra recorded at defect and clean region, showing drastic changes in the carrier lifetime. (a) (b) (c) Fig. 4 (a) Optical micrograph of the surface defect and micro-cracks. (b) Raman map, showing GaN, peak intensity variation near the defect region and (c) stress-induced spectral changes near the defect region. (a) (b) (c) Fig. 5 (a) Large area PL map of a commercially available LED display panel, showing defective pixels. (b) and (c) High-resolution PL maps of normal and defective pixels showing brightness variations. (a) (b) (c) micro-cracks (Fig. 4a). Raman mapping of the E2 phonon mode of GaN in the vicinity of these micro-pits (Fig. 5b) and micro-cracks (Fig. 5c) showed a redshift compared to the surrounding defect-free regions (Fig. 4b). This redshift indicates the presence of tensile stress associated with these structural defects. Micropits are often linked to threading dislocations originating during the epitaxial growth process,[3] which can introduce strain fields in the surrounding lattice. PHOTOLUMINESCENCE MAPPING OF LED DISPLAY PANEL Large-area PL mapping of a commercially available LED display panel (Fig. 5a) success- fully identified individual defective pixels exhibiting low brightness or no emission. Subsequent high-resolution PL mapping (5 µm step size) of both defective and normal pixels (Fig. 5b)
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