A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2025 | VOLUME 27 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org BACKGROUND AND HISTORY OF THE U.S. CHIPS ACT AN ION MICROSCOPE FOR IMAGING AND SIMS NANOANALYTICS SOLDER JOINTS UNDER VARYING TEMPERATURES AND SALINITIES SILICON PHOTONIC FA USING NEAR INFRARED MICROSCOPY 4 16 2 8
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2025 | VOLUME 27 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org BACKGROUND AND HISTORY OF THE U.S. CHIPS ACT AN ION MICROSCOPE FOR IMAGING AND SIMS NANOANALYTICS SOLDER JOINTS UNDER VARYING TEMPERATURES AND SALINITIES SILICON PHOTONIC FA USING NEAR INFRARED MICROSCOPY 4 16 2 8
edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 ABOUT THE COVER Laser-crafted sci-fi castle. This image showcases a large 100 μm-wide bulk structure holding 19 individual lamellae, each precisely targeting a specific memory layer within a 3D NAND stack. Photo by Arun Prabha, Zeiss Microscopy. First Place Winner in Black and White Images, 2024 EDFAS Photo Contest. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2025 | VOLUME 27 | ISSUE 2 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS A Novel Ion Microscope for HighResolution Ion Imaging and SIMS Nanoanalytics with Precise Sample Navigation Peter Gnauck, Alexander Ost, and Torsten Richter This article introduces a novel system that integrates high-resolution 2D/3D imaging and secondary ion mass spectrometry nanoanalysis. Author Guidelines Author guidelines and a sample article are available at edfas. org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 8 2 GUEST EDITORIAL Steve Herschbein 24 PAINE CONFERENCE Michael DiBattista 26 2025 PHOTO CONTEST 27 2025 VIDEO CONTEST 28 DIRECTORY OF FA PROVIDERS Rosalinda Ring 30 EDUCATION NEWS Navid Asadi 32 LITERATURE REVIEW Michael R. Bruce 34 PRODUCT NEWS Ted Kolasa 37 ASM FACT SHEET 39 TRAINING CALENDAR Rosalinda Ring 42 GUEST COLUMN Paul Hale 44 ADVERTISERS INDEX Study about the Corrosion of SAC Solder Joints Under Various Conditions of Temperature and Salinity A. Guédon-Gracia, K.E. Akoda, J.-Y. Delétage, and H. Frémont Solder joints were electrically and mechanically tested and aged in a salt spray chamber to test the dynamics of the corrosion mechanism. 16 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Silicon Photonic Failure Analysis using Near Infrared Microscopy Arpan Dasgupta An emerging silicon photonic technique, near infrared microscopy, is proving useful for isolating unexpected light losses as a first pass. 4 16 8
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 2 One of the lasting legacies of the 2020 COVID-19 crisis was the economic impact, still felt nearly three years after the general recovery. The semiconductor industry as a whole registered some of the greatest restart issues. Severe supply chain disruptions became the limiting factor in the production of everything from automobiles to home appliances to computers, and even defense and general infrastructure items. The pundits blamed it largely on the complexity of fab restart and workforce issues, but these only account for part of the delayed recovery and continued shortfall in select products. Increased component complexity, rapidly shifting demand profiles, and capacity constraints in a number of niche and leading-edge technologies were not immediately recognized or fully understood by outside observers. COVID was a convenient trigger for an industry primed for problems, as many of the underlying factors were 15 years or more in the making. For example, regular progression in wafer size came to an end with 300 mm. The fabless model continued to gain momentum, but foundry capacity, largely centered in Asia, failed to keep pace. At the ultra-high end, only a handful of manufacturers made it to FinFETs, and only TSMC, Samsung, and a struggling Intel are likely to go beyond to gate-all-around. The cost of extreme ultraviolet lithography for sub 7 nm has pushed the cost of new fabs beyond $20 billion USD, simply too much for most players. And the lure of higher end technologies and the subsequent abandonment of certain legacy products has caused shortages of essential, but “unglamorous” components. While the U.S. still retains leadership in microchip design, domestic chip manufacturing dropped to an all-time low of around 11% of worldwide demand. Package substrate manufacturing and assembly hovers near zero. By comparison, the U.S. supplied close to 40% of silicon in 1990 and considerably more in the decades prior. The Defense Department, Intelligence and Commerce, among others, became increasingly concerned about essential high-end chips produced overseas, the possible impact on national security, and overall economic competitiveness. Several individual U.S. states saw the growing problem and led by example ahead of federal action, providing proof that government/industrial cooperation does work. New York incentives landed SEMATECH and GlobalFoundries (GFS), and talks with Micron and Wolfspeed followed. Texas locked in Samsung, Arizona signed the first of several TSMC fabs, and Ohio was in talks with Intel. The CHIPS Act ($52B in contract grants), part of the larger $280B bipartisan CHIPS and Science bill, was finally signed into law on August 9, 2022, to operate MAY 2025 | VOLUME 27 | ISSUE 2 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL THE CHIPS ACT AND ITS IMPACT ON THE SEMICONDUCTOR INDUSTRY AND ANALYTICAL LABS Steve Herschbein, retired IBM/GFS steven.herschbein@gmail.com edfas.org (continued on page 25) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2025 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Herschbein
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 4 EDFAAO (2025) 2:4-7 1537-0755/$19.00 ©ASM International® SILICON PHOTONIC FAILURE ANALYSIS USING NEAR INFRARED MICROSCOPY Arpan Dasgupta GlobalFoundries, Malta, New York arpan.dasgupta@globalfoundries.com INTRODUCTION Silicon photonics has emerged as a promising solution for on-chip communication to improve computational systems in data centers.[1] High volume manufacturing of functional and reliable photonic integrated circuits (PICs) is key to delivering a co-packaged optics (CPO) solution with compute ICs. GlobalFoundries’ silicon photonics approach provides a monolithic platform using silicon-oninsulator (SOI).[2] Both silicon optics and silicon electronics are realized on the same chip, including a cavity for III-V laser light source to be attached after the wafer fabrication process.[3] The high reflective index of silicon (n = 3.5) or silicon nitride (n = 2.05) waveguides embedded in oxide (n = 1.5) allow for on-chip light distribution with relatively small bending waveguides radii essential for the design of very compact PICs. Electrical-to-optical light conversion is accomplished by using Mach-Zehnder modulators or micro-ring modulators fabricated from silicon wave guides. These junction-based modulators are able to switch the light in a range of up to 50 GHz. Light detection is accomplished by integrating a Ge photodetector in the receiver. Because Ge has a lower band gap than Si, light in the O-band, the C-band, and the L-band is absorbed and converted into an electrical signal.[4] Lastly, the optical I/O from the chip into the fiber and from the fiber into the chip is realized with horizontal edge couplers. Deep trenches with exact dimensions are etched into the silicon wafer forming V-grooves. Single mode fibers can then be placed in the V-grooves, allowing the precise alignment of fiber core and Si waveguide with minimal insertion and return losses.[5] The key elements of GlobalFoundries’ Fotonix offering are illustrated in Fig. 1.[6] Failure analysis techniques are still at their infancy when it comes to silicon photonics.[7] This article focuses on one emerging technique, near infrared microscopy (IR), which is proving to be very useful for isolating unexpected light losses as a first pass. Near IR microscopes are not new to the semiconductor industry. Historically, they have been used to image silicon dies from the backside of the chip, which is externally illuminated by an infrared lamp. One advantage with the near IR range is that unlike mid-range or far-range IR, conventional glass optics work just as well with near IR. This allows the user to utilize conventional microscopes to achieve high magnification optics to isolate and characterize light paths. Most near IR microscopes work with an InGaAs sensor which is Fig. 1 GlobalFoundries Fotonix provides a library with a wide variety of photonic devices that are built on SOI wafers—active and passive photonics components using CMOS-compatible processes, RF-friendly BEOL, and low-loss optical I/O (V-groovespot size converter) for high fiber count. The optical devices are tailored specifically for the near infrared range (C-band and O-band).
edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 sensitive in the 0.9-1.7 μm wavelength range. Luckily for Si photonics, both the C-band (1550 nm center wavelength) and O-band (1310 nm center wavelength) fall within the sensing region of the IR microscope. IR MICROSCOPE EXPERIMENTAL SETUP Figure 2 shows a simplified overview of a near infrared diagnostic setup. A packaged module with an exposed silicon die would be placed under a microscope. The microscope can be any conventional microscope, but with a near IR sensor attached to it. The packaged module would be connected to the proper instrumentation to run the chip. In most cases the instrumentation involves using a laser source in the C or O band in conjunction with a polarizer. THE BASICS: WAVEGUIDE IMAGING UNDER LIGHT INJECTION Figure 3 demonstrates an example of an infrared image taken of a simple waveguide on a PIC under operation. The infrared camera was able to trace out the light path. In an ideal scenario, none of the light traveling through the waveguide should be able to leak out. But due to fabrication realities, there is always a little bit of line edge roughness, which leads to tiny amounts of light leaking out and illuminating the waveguide, thereby tracing the light path. Figure 3 demonstrates an example of a bend in the waveguide. FAILURE MODES CASE STUDY 1: DETECTING PACKAGING FAILURES Sometimes, the silicon itself may be operating as expected, but an error in the packaging process prevents the light from coupling into the silicon in the first place. Such errors can be detected using the infrared microscope. Figure 4a shows an example of an edge coupler where the light is properly coupled into the silicon chip. This is used as a baseline, which is used for comparing modules that are not performing as well. Figure 4b is an example of an edge coupler where the performance (a) (b) Fig. 2 Setup for infrared microscopy of photonic integrated circuit dies. Fig. 3 Example of waveguide imaging of a PIC die using IR microscope. Fig. 4 (a) Infrared image of a spot size coupler with good fiber attach process. (b) Infrared image of a spot size coupler with fiber attach excursion.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 6 was poor. Compared to a known good sample image, the scattering signature is markedly different. This allowed the failure analysis team to focus their efforts to look for package failures, driving deeper to root cause. For cases like these, it is important to have a known good sample to be used for comparisons. CASE STUDY 2: DETECTING IN-OPERATION FAILURES Failure in modules during operation is first detected by a drop in insertion loss greater than what is expected. In such cases, one of the best uses of the infrared scope is narrowing down the list of suspects in an optical path. One of the more recent failure modes the GlobalFoundries team has reported in literature is the permanent damage that occurs in our PICs when the input power goes beyond a certain threshold.[8] Using the infrared microscope, we were able to isolate the failure in the optical path to be at the silicon-based spot size converters, which is used to bring in light from an external fiber to the silicon chip (Fig. 5). The primary mechanism is due to the two-photon absorption that occurs in silicon waveguides. Siliconnitride based spot size converters which do not exhibit the two-photon absorption problem are better suited for high optical power applications. CASE STUDY 3: DETECTING YIELD DETRACTORS Some failure modes occur due to processing yield issues. In such cases, the first step toward driving to root cause is narrowing down the area on the chip. In this case, the IR images between a good and bad module clearly distinguish the failure mode location(s) in the optical path (Fig. 6). This information was later fed back to the FA team to dig deeper into looking for physical faults. CONCLUSION The near IR microscope is a powerful failure analysis tool to assist in silicon photonics applications. Its primary function is to provide the first signals and narrow down the scope of area where more detailed analysis needs to be performed. Localization of faults is the main strength in terms of failure analysis. With its ability to scale up to any microscope optics, the technique lends itself to a wide flexibility depending on the application. It is expected that the usefulness of this technique will continue as the photonics ecosystem evolves. REFERENCES 1. V. Gupta: “GLOBALFOUNDRIES Silicon Photonics,” Consortium for On-Board Optics (COBO), September 1, 2020. Fig. 5 (a) False color infrared image of spot size converter at lower power levels. (b) Infrared image after the permanent damage of coupler at high power levels. Fig. 6 (a) False color infrared image of known good PIC die under operation. (b) Infrared image of a yield detractor die at similar location. (a) (a) (b) (b)
edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 2. M. Rakowski, et al.: “45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for Next-generation, Low Power and High Speed Optical Interconnects,” T3H.3, 2020 Optical Fiber Communications Conference (OFC), March 8-12, 2020. 3. Y. Bian, et al.: “Hybrid III-V Laser Integration on a Monolithic Silicon Photonic Platform,” M5A.2, 2021 Optical Fiber Communications Conference (OFC), June 6-10, 2021. 4. J. Ayala, et al.: “Integrating a High Performance Ge Photodiode into a CMOS Compatible Flow for a Full Monolithic Silicon Photonics Solution,” 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), May 6-9, 2019. 5. K. Giewont, et al.: “300-mm Monolithic Silicon Photonics Foundry Technology,” IEEE J. of Select Topics in Quantum Electronics, 2019, 25(5), p. 1-11. 6. Y. Bian, et al.: “3D Integrated Laser Attach Technology on a 300-mm Monolithic CMOS Silicon Photonics Platform,” IEEE J. of Select Topics in Quantum Electronics, 2023, 29(3), p. 1-19. 7. F.H. Baumann, et al.: “Failure Analysis of Photonic Integrated Circuits,” EDFA, 2023, 25(3), p. 23-30. 8. A. Dasgupta, et al.: “High Power Performance Assessment of LowLoss Spot Size Converter based on Self-aligned Passive Fiber Attach Process,” 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), May 28-31, 2024. ABOUT THE AUTHOR Arpan Dasgupta is a principal engineer in the photonics packaging and test team at GlobalFoundries. His expertise lies in co-packaged optics, fiber-to-chip couplers and diagnostic capabilities. Prior to joining GF, he was a researcher at UCLA CHIPS where he worked on heterogeneous integration. Dasgupta has completed his M.S. at ECE from UCLA and bachelor’s degree at the Heritage Institute of Technology. CALL FOR EDFAS STUDENT BOARD MEMBER The ASM Electronic Device Failure Analysis Society is seeking applications for its student board member position. Applications are due May 19. The student must be a STUDENT BOARD MEMBER registered undergraduate or graduate during the 20252026 academic year and must be studying or involved in research in the field of failure analysis for the electronic/ semiconductor industry. For more information visit asminternational.org/edfas/ board-nominations.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 8 A NOVEL ION MICROSCOPE FOR HIGH-RESOLUTION ION IMAGING AND SIMS NANOANALYTICS WITH PRECISE SAMPLE NAVIGATION Peter Gnauck, Alexander Ost, and Torsten Richter Raith GmbH, Dortmund, Germany peter.gnauck@raith.com EDFAAO (2025) 2:8-12 1537-0755/$19.00 ©ASM International® INTRODUCTION Understanding nanoscale materials and their transformation processes requires advanced techniques with high lateral resolution and sensitivity. Recent advancements in focused ion beam (FIB) technologies, combined with secondary ion mass spectrometry (SIMS), have significantly enhanced the ability to visualize and analyze nanoscopic 3D structures. SIMS, a powerful analytical technique, employs primary ions to sputter sample surfaces, generating secondary ions that are separated by a mass analyzer to provide detailed elemental information. This technique offers high sensitivity and a wide dynamic range, making it indispensable for recording mass spectra, depth profiling, and 2D/3D imaging. The integration of high-resolution ion microscopy, in-situ SIMS, and a high-precision laser interferometer stage has facilitated the correlation of topographic and chemical information at the highest spatial resolution, thereby advancing our understanding of materials in various fields, including semiconductor technology.[1] This article introduces a novel system that integrates high-resolution 2D/3D imaging and SIMS nanoanalysis. This system uniquely combines a liquid metal alloy ion source (LMAIS),[2] a dedicated magnetic sector SIMS unit, and a laser interferometer-controlled sample stage. The LMAIS technology enables the emission of multiple ion species simultaneously from a single source, which are then separated using a Wien filter. This setup allows for the quick selection and switching between ion species, facilitating the use of heavy ions like Bi+ or Au+ for sample delayering, and lighter ions like Li+ or Si2+ for high-resolution imaging.[3] These capabilities enable the generation of 3D volume reconstructions of samples from individual image planes. The maximum field of view for all ions is 200 µm at 35 keV landing energy. The SIMS unit is equipped with an extraction optic that transfers the generated secondary ions through a mass analyzer to a focal plane detector, allowing the parallel acquisition of full mass spectra for each scanned pixel within the field of view. This system’s ability to switch between reactive primary ion species to maximize positive or negative ionization of sputtered particles further enhances its analytical capabilities.[4] The small beam diameter of the lightest primary ions (Li+ or Si2+) supports high spatial resolution imaging in SIMS (<20 nm), while the low penetration Fig. 1 Schematic setup of the instrument: Vertical FIB column with LMAIS, high precision laser interferometer stage and SIMS unit with extraction and transfer optic, magnetic sector, and continuous focal plate detector.
edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 depth of heavy Bi+ and Au+ ions ensures excellent depth resolution. To meet the demands of nanoanalytics or nanofabrication the sample stage position is measured with displacement interferometers using a highly stabilized helium-neon laser with ≤1 nm resolution. The precision and resolution of the interferometric measurement, combined with the capabilities of the hybrid positioning system, ensure accurate placement of the point of interest, with positioning increments ranging from just a few nanometers to the scale of wafers. The combination of LMAIS FIB, a laser interferometer stage with CAD-based navigation, and a magnetic-sector SIMS presents significant potential for automated workflows, particularly for buried defect review and residue detection (Fig. 1). This article details the key features and setup of this novel analytical ion microscope system, showcasing its application in correlative 2D and 3D imaging of microelectronics samples. The results demonstrate that this system represents a significant advancement in nanoanalytics, offering capabilities beyond conventional methodologies by integrating LMAIS technology with a stable stage and SIMS unit for highresolution analytical imaging. This study presents the results of correlative 2D and 3D imaging using the recently developed nanoanalysis system. The system, which integrates LMAIS technology, a stable laser interferometer-controlled stage, and a dedicated magnetic sector SIMS unit, demonstrates significant advancements over conventional methodologies for sample analysis. ENHANCED IMAGING CAPABILITIES The integration of LMAIS technology allows for the simultaneous emission and rapid switching between multiple ion species. This capability is particularly advantageous for applications requiring different ion species for specific tasks, such as using heavy ions like Bi+ or Au+ for delayering and lighter ions like Li+ or Si2+ for high-resolution imaging (Fig. 2). The ability to switch ions within seconds significantly improves workflow efficiency and flexibility. The high spatial resolution imaging achieved with lighter primary ions (Li+ or Si2+) (<20 nm) and the excellent depth resolution provided by heavy ions (Bi+ and Au+) enhance the system’s capability to generate detailed 3D reconstructions of samples (Fig. 3). In this example, delayering was performed using 35 keV Bi⁺ ions, while imaging was conducted with 35 keV Li⁺ ions. Heavy ions like Au⁺ and Bi⁺ have lower penetration into the sample compared to Ga⁺, resulting in smoother surfaces. The combination of high spatial resolution imaging with lighter primary ions (Li⁺ or Si2⁺) (<20 nm) and the excellent depth resolution provided by heavy ions (Bi⁺ and Au⁺) enhances the system’s capability to generate detailed 3D reconstructions of samples. A Python code was used to visualize the image data in 3D as a lateral cross-sectional view.[3] CORRELATIVE 2D AND 3D IMAGING Copper indium gallium selenide (CIGS) solar cells are high-efficiency, rigid or flexible thin-film photovoltaics. Rubidium (Rb) enrichment enhances their efficiency and stability by improving the charge carrier concentration as well as increasing grain growth and reducing crystallinity defects, leading to better carrier collection. This advancement makes CIGS a strong alternative to siliconbased solar cells. The combination of high-resolution ion Fig. 2 Bismuth and lithium ions are used alternately. Appropriate Bi beam milling strategies are effectively employed to ensure smooth and uniform delayering of the sample. Intermittent imaging with lithium ions delivers high-resolution images between respective milling steps. Fig. 3 3D nano-reconstruction of the sample using SE images acquired with ions from GaBiLi ion source. The precision of the laser interferometer stage ensures a perfect alignment of the acquired images, (FOV 5 µm).
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 10 microscopy and in-situ SIMS allows for the precise correlation of topographic and chemical information of the CIGS solar cell. The ability to acquire full mass spectra for each scanned pixel within the chosen field of view enables a comprehensive analysis of the solar cell and especially of the Rb distribution (Figs. 4 and 5). This functionality is crucial for applications in microelectronics, where detailed high-resolution elemental and structural information is necessary to understand the material properties and identify defects. AUTOMATION AND WORKFLOW EFFICIENCY The integration of a laser interferometer stage with CAD-based navigation and the magnetic-sector SIMS unit offers significant potential for automated workflows. This setup is particularly beneficial for applications such as buried defect review and residue detection, where precise and repeatable measurements are essential. The high precision of the laser interferometer stage ensures accurate alignment of acquired images, facilitating the generation of precise 3D volume reconstructions (Figs. 3 and 6). Additionally, the system supports navigation on KLARF files, enabling the analysis of defects detected by inspection tools. This capability allows for seamless correlation of defect data with SIMS imaging and chemical analysis, enhancing defect characterization and process optimization (Fig. 7). APPLICATIONS IN MICROELECTRONICS These results demonstrate the system’s effectiveness in analyzing microelectronics samples. The detailed 2D and 3D imaging capabilities allow for the identification and analysis of structural and elemental features at nanoscale resolution. This level of detail is critical for advancing the understanding of material properties and improving the design and manufacture of microelectronic devices. (a) Fig. 4 (a) SE image of a CIGS solar cell and (b) corresponding SIMS spectrum. Fig. 5 (a) 85Rb and (b) 115In distribution in the CIGS solar cell. (c) 2D map of the 85Rb+87Rb and 113In+115In isotopes superimposed on the SE signal. The Rb is confined in the grain boundaries only, (FOV 20 µm). (b) (c) (a) (b)
edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 HIGH-RESOLUTION SIMS FOR PROCESS CONTROL High-resolution SIMS plays a pivotal role in process control within the microelectronics industry. The integration of SIMS with high-resolution ion microscopy offers unparalleled sensitivity and precision for elemental analysis, which is critical during various stages of device fabrication. LAYER COMPOSITION ANALYSIS High-resolution SIMS enables the precise determination of layer compositions in multilayered devices. This capability is complemented by high-resolution elemental imaging at <20 nm resolution, allowing for detailed visualization and mapping of elemental distributions at the nanoscale (Fig. 8). Such precision is particularly important for thin films, where uniformity and stoichiometry are crucial for optimizing device performance and ensuring reliability. IMPURITY DETECTION The detection and quantification of trace impurities in semiconductor materials are facilitated by SIMS’ high sensitivity. This ensures adherence to strict quality control standards and minimizes the risk of defects. DEPTH PROFILING SIMS provides high-depth resolution profiles of dopant distributions, which are essential for understanding diffusion processes and optimizing implantation techniques. This capability is vital for the development of advanced doping strategies in modern semiconductor devices. Fig. 8 High resolution SIMS mapping of a 65 nm CMOS process node logic device in a LGA flip chip package. The backside silicon substrate has been removed with a combination of CNC grinding and polishing followed with argon ion beam processing and xenon difluoride etching to allow direct access to the shallow trench isolation dielectric layer and the tungsten source drain contacts of the transistor region. 28Si + 29Si + 30Si in blue, all Ti isotopes in red. Fig. 6 3D reconstruction of the 85Rb+87Rb (orange) and 113In+115In (gray) isotopes, (FOV 20 µm). Fig. 7 The laser interferometer stage allows for precise sample navigation on CAD files.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 12 PROCESS MONITORING The integration of high-resolution SIMS in process monitoring workflows enables real-time feedback on material deposition, etching, and cleaning processes. This accelerates the optimization of fabrication parameters and enhances yield rates. DEFECT ANALYSIS SIMS contributes significantly to the analysis of buried defects by providing detailed elemental mapping. Combined with laser interferometer stage navigation, it ensures accurate localization and characterization of defects, aiding in process refinement. CONNECTIVITY WITH OTHER PROCESS CONTROL TOOLS The system’s design includes connectivity capabilities with other process control tools such as inspection tools, CD SEMs, and defect review SEMs. This interoperability facilitates seamless integration into existing workflows, enabling comprehensive analysis by correlating SIMS data with inspection results, critical dimension measurements, and defect characterization. Such connectivity enhances the decision-making process and streamlines quality assurance protocols. By incorporating high-resolution SIMS into process control protocols, manufacturers gain a robust tool for ensuring the reliability and performance of microelectronic devices. The synergy of SIMS with advanced imaging technologies exemplifies its transformative potential in next-generation semiconductor manufacturing. FUTURE DIRECTIONS The novel combination of LMAIS technology, a stable stage, and a SIMS unit paves the way for nanoanalytics beyond conventional methodologies. Future research can explore further optimization of the system for various applications, including the integration of additional ion sources or detectors to expand its analytical capabilities. Additionally, the development of more sophisticated automated workflows will enhance the system’s efficiency and application range. CONCLUSION By incorporating high-resolution SIMS into microelectronics workflows, manufacturers achieve unprecedented precision and insight into fabrication processes. Its adaptability for diverse tasks, seamless integration with complementary tools, and unparalleled analytical power make it indispensable for optimizing material properties, ensuring quality, and driving innovation in next-generation semiconductor manufacturing. REFERENCES 1. J.-N. Audinot, et al.: “Highest Resolution Chemical Imaging based on Secondary Ion Mass Spectrometry Performed on the Helium Ion Microscope,” Rep. Prog. Phys., 2021, 84, 2021, p. 105901, doi.org/ 10.1088/1361-6633/ac1e32. 2. Bischoff, et al.: “Liquid Metal Alloy Ion Sources—An Alternative for Focused Ion Beam Technology,” Appl. Phys. Rev. 3, 2016, p. 021101, doi.org/10.1063/1.4947095. 3. A. Nadzeyka, et al.: “Focused Ion Beams from GaBiLi Liquid Metal Alloy Ion Sources for Nanofabrication and Ion Imaging,” J. Vac. Sci. Technol. B, 41, 2023, p. 062802, doi.org/10.1116/6.0002918. 4. O. De Castro, et al.: “npSCOPE: A New Multimodal Instrument for In Situ Correlative Analysis of Nanoparticles,” Anal. Chem., 93, 2021, p. 14417–14424, doi.org/10.1021/acs.analchem.1c02337. ABOUT THE AUTHORS Peter Gnauck earned his Ph.D. in physics from the University of Tübingen in 2000. He worked at Carl Zeiss Microscopy for over two decades in various roles, specializing in electron microscopy and focused ion beam (FIB) technology. He then joined KLA as a product marketing manager for e-Beam overlay. Since 2024, he has been serving as global business development manager for FIB/ SEM systems at Raith GmbH. Alexander Ost has worked as an applications development engineer at Raith since March 2023. His main activities at Raith include performing customer demos and sample analysis on the Ionmaster system, developed in collaboration with the Luxembourg Institute of Science and Technology (LIST). Just before joining Raith, he completed his Ph.D. in physics at LIST and the University of Luxembourg on SIMS with focus on correlative high-resolution 2D as well as 3D imaging workflows and focused ion beam sputtering mechanisms. Torsten Richter joined the Raith Group as the VELION product manager in 2019 to oversee all market activities for FIB-related products. Most recently, he transitioned into the position of FIB program manager to foster nanoanalytics and ion microscopy. Richter obtained a diploma in physics from the University of Dortmund. Prior to joining Raith, he held similar positions at other nanotechnology companies, primarily in the field of nanoanalytics and surface characterization.
edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 NOTEWORTHY NEWS FIB SEM MEETING 2025 The 17th annual FIB SEM Meeting, to be held May 6-7, is returning to the Science and Engineering Hall at George Washington University in Washington, DC. The 2025 FIB SEM will feature presentations, tutorials, and posters by FIB users and vendors, highlighting new applications and the latest technology. The event offers plenty of technical content as well as opportunities for informal discussions with FIB colleagues. Continuing this year will be student awards for best oral and poster presentations. For more information, visit fibsem.net or email keana.scott@nist.gov or fibsem2025@fibsem.net. IPFA 2025 The 32nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) will be held August 5-8 at the Spice Convention Centre in Penang, Malaysia. The event will focus on cutting-edge research in failure analysis, reliability, and specialized technology within integrated circuits. Topics include advanced fault isolation techniques, physical and package-level failure analysis, transistor reliability, ESD, latch-up, and the integration of AI for failure detection and reliability assessments. The symposium is technically sponsored by the IEEE Electron Devices Society. For more information, visit the IPFA website at ipfaieee.org/2025.
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 16 STUDY ABOUT THE CORROSION OF SAC SOLDER JOINTS UNDER VARIOUS CONDITIONS OF TEMPERATURE AND SALINITY A. Guédon-Gracia, K.E. Akoda, J.-Y. Delétage, and H. Frémont IMS lab, Université de Bordeaux, CNRS, Talence, France alexandrine.gracia@u-bordeaux.fr EDFAAO (2025) 2:16-23 1537-0755/$19.00 ©ASM International® INTRODUCTION The durability of electronic assemblies is determined by the mechanical reliability of the solder joints against different degradation factors. A harsh marine environment associated with mechanical and electrical stresses is one of the environmental effects responsible for degrading the fatigue life of lead-free solder joints made of tin, silver, and copper (Sn-Ag-Cu), called SAC solder joints, in real-life applications.[1] These solder joints make the junction between the printed circuit and the component. Hence, they are one of the significant structures in electronic devices, which not only serve as physical connections but also transfer electricity and dissipate Joule heat.[2] Wang et al.,[3] in a comparative study of the corrosion behavior of SAC305 solder material and solder joints using a salt spray test according to ASTM B117-09 standard (5% NaCl at 35°C)[4] revealed that the corrosion risk in solder joints on a copper pad increased compared to that of lead-free solder alloys due to the galvanic corrosion process. Previous studies on SAC305 solder material alloy demonstrated that temperature has a significant effect on the dynamics of the corrosion mechanism of SAC305 solder alloy under salt spray test conditions.[5-7] In this paper, the influence of the salinity rate is studied. Moreover, a failure criterion on the corroded area is determined. EXPERIMENTAL PROCEDURE VEHICLE TEST The test vehicle comprises identical size chip resistors (1210) soldered with SAC305 lead-free solder on an FR4 board (Fig. 1). A copper defined pad is used with electroless nickel/immersion gold (ENIG) finish. SALT SPRAY CONDITIONS The electronic assemblies are exposed to a salt spray environment in a salt spray chamber, Ascott CC450Ip for 96 hr and then for 192 hr. The advantages of the salt spray chamber are the homogeneity of the temperature and the salt spray in the chamber and therefore the reproducibility of the test conditions. Three exposure temperatures (25°C, 35°C, 45°C) for three salinity rates (3.5%, 5%, 6.5% of NaCl) are studied. Fig. 1 Printed circuit board with ceramic resistors.
edfas.org 17 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 ELECTRICAL AND MECHANICAL MEASUREMENTS In general, the failure criteria defined for solder joints are electrical continuity and mechanical strength. Electrical measurements are carried out using an Agilent multimeter in a two-wire ohmmeter to evaluate the electrical continuity provided by solder joints. Using a two-wire ohmmeter in this study is sufficient to measure the fixed electrical failure criterion, resistance superior to 100 kΩ. Shear tests are performed using a Dage series 4000 shear tester on the three resistors for each exposure time at each condition of the salt spray test. The final shear force value represents the average obtained for these three sheared resistors. It should be noted that the failure criterion is determined during the shear testing according to the MIL-STD-883 standard. This criterion indicates that a minimum force of 5 kg is sufficient to shear the support component.[8] Table 1 lists the parameters used for the shear tests. FAILURE ANALYSIS After being removed from the chamber, components are washed in deionized water and dried with a stream of clean, compressed air. Then the cross-sections are prepared using SIC papers (P1000-P1200) and finely polished using diamond slurries (9 μm-6 μm-3 μm-1 μm). The crosssections of the solder joints are analyzed with an optical microscope and a scanning electron microscopy (SEM) equipped with energy dispersive x-ray (EDX). An observable corrosion criterion is based on the color change of the solder from the initial state (silver gray) to the corroded state (dark gray) previously defined in Akoda et al.[5-6] The dark gray color of the corrosive state is considered to be a loss of solder material. The chemical composition and distribution of the elements in the corroded area are determined by SEM. Four solder joints are observed for each test condition. The percentage of corroded surface solder joint is defined as the ratio of the surface of the corroded solder joints area after the salt spray test to the total surface of solder joints. RESULTS AND DISCUSSION ELECTRICAL MEASUREMENT The electrical resistance of SAC305 solder joints is measured before and during the salt spray test. Their values are about 0.8 Ω ± 0.2 Ω, which is close to 0 Ω. No evolution is observed after 192 hr in salt spray test. Thus, the solder joints are electrically intact at the end of the aging. No electrical failure is observed. SHEAR TEST The force necessary to shear the resistor solder joints of test vehicle resistors is plotted in Fig. 2 for each salinity rate. The shear strengths decrease with increasing corrosion time, temperature, and NaCl concentration. The temperature and the salinity rate have a significant effect on shear force and therefore on the mechanical resistance of the solder joints. The yellow line on the graphs corresponds to the failure criterion of 5 kg defined by the standard. However, after 96 hr of salt spray testing, mechanical failures are detected only for 6.5% NaCl and at 35°C and 45°C. All the curves are linearized. This method can be used to determine the time to mechanical failure according to the chosen criterion. The results consistent with these from Wang et al.[3] where the authors studied the effects of corrosion on the mechanical strength of SAC405 lead-free solder joints. K. Yokoyama et al.[9] demonstrated that the reliability evaluation of lead-free solder alloy should be conducted for various combinations of environments and applied stresses where they investigated the fracture behavior of SAC305 alloy subjected to a constant tensile-loading test in NaCl aqueous solution at room temperature. SOLDER JOINT MORPHOLOGY AND CHEMICAL COMPOSITIONS OF THE CORROSION PRODUCT Figure 3 shows the observed corrosion morphology and the corroded area behavior for optical analyses of SAC305 solder joints at different times and aging temperatures. Corrosion can be observed after several exposure times to salt spray, depending on the test conditions. Although the samples are subjected to a homogeneous salt spray, and a priori to isotropic etching the solder joint surface is not uniformly attacked. The corrosion site is different from one solder joint to another. Table 1 Shear test parameters Parameters Settings Range 100.0 kg Test speed 100.0 μm/s Test load 0.5 kg Max test load 40.0 kg Land speed 500.0 μm/s Shear height 200.0 μm Over travel 100.0 μm Max shear distance 5000.0 μm
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 18 Having defined the visible corrosion criterion as a loss of solder material, CAO AutoCAD software is used to estimate the percent of eroded solder joint area at the different exposure times. An example estimation of the percentage of the corroded area of a solder joint at 25°C after 72 hr is shown in Fig. 4. For each exposure time condition, the percentage of corroded area considered represents the average of the corroded area percentage for four observed joints. Table 2 shows an example estimation of the average percentage of the corroded area for four joints observed at 25°C after 96 hr. Statistical information on the average percentage of corroded area for the four joints observed allows for a sufficient representation of the results. The results of the experiment for 5% NaCl tests are summarized in Fig. 5. The percent of corroded solder joint area increases with increasing temperature. According to the EDX analysis (Fig. 6), this corrosion area of SAC305 solder joints contains mainly Sn, O, and Cl-. DETERMINATION OF A FAILURE CRITERION ON THE CORRODED AREA The mechanical test results are correlated with the corroded surface analysis. The time to failure (TTF) after shear tests is determined for each temperature by extrapolating the trend curves in Fig. 2. Then, using the linear trend curves in Fig. 5, the percentages of corroded solder joint area at these times could be estimated for each temperature. Table 2 summarizes the estimated TTF values and the percentage of corroded solder joint area estimation for each temperature at 5% NaCl. It is noteworthy that the time to failure resulting from a corroded surface remains relatively consistent across all temperatures examined. Considering the potential inaccuracies associated with the measurement method, this observation is significant. Consequently, it enables us to establish a time to failure based on a percentage of the average corroded solder joint area (61%). Fig. 2 Shear force evolution during the salt spray tests.
edfas.org 19 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 VERIFICATION OF THE FAILURE CRITERION ON THE CORRODED ZONE SURFACE Additional salt spray tests were carried out to verify this failure criterion in the corroded zone. Some electronic assemblies have been submitted to salt spray test for 192 hr. The TTF determined by the shear force measurements is 180 hr (Fig. 7). However, for this exposure time, 50% of the solder joint area is corroded. So, it can be considered that the failure criterion for the corroded zone is correct. CONCLUSION The dynamics of corrosion on SAC305 solder joints subject to salt spray (5% NaCl) test were investigated in this study. The impact of salinity rate and the temperature were measured on the shear force and on the corroded surface of the solder joint. No electrical resistance variation was observed with and without corrosion. Thus, another parameter needs to be measured to quantify the impact of corrosion on the reliability of solder joints. The force necessary to shear the components and the corroded surface of the solder joint were chosen. The results show that the temperature accelerates the corrosion mechanism. Moreover, the salinity rate has a significant effect on the evolution of the corrosion. According to the SEM and EDX investigation of solder joints Fig. 3 Corroded solder joints. Table 2 Estimated values of TTF and percentage of corroded solder joint area T, °C Time, hr % solder joint corroded area 25 192 51 30 203 57 35 183 69 40 129 64 45 112 65 Fig. 4 Example estimation of the percentage of the corroded area of a solder joint at 25°C after 72 hr. Fig. 5 Percent of corroded solder joint area as a function of the exposure time at 5% NaCl. (a) (b) (c)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 20 Fig. 6 EDX of solder joint resistor (5% NaCl at 35°C) after 48 hr in salt spray chamber. Fig. 7 Evolution of the shear force (left) and of the corroded solder joint (right).
edfas.org 21 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO.2 microsections, Sn, O, and Cl- were found in the corrosion surface area. The mechanical behavior and the percentage of corroded area of the solder joints are clearly correlated. This has made it possible to define a failure criterion on the corroded surface of the solder joints. REFERENCES 1. M. Abueed, et al.: “Combined Creep and Fatigue Loadings on SAC305 Solder Joint,” SMTA International Conference 2020. 2. X. Long, et al.: “An Insight into Dynamic Properties of SAC305 Lead-free Solder under High Strain Rates and High Temperatures,” Int. J. Impact Eng., 2023, 175, p. 104542, doi.org/10.1016/ j.ijimpeng.2023.104542. 3. M. Wang, J. Wang, and W. Ke: “Corrosion Behavior of Sn-3.0Ag-0.5Cu Lead-free Solder Joints,” Microelectron. Reliab., 2017, 73, p. 69‑75, doi.org/10.1016/j.microrel.2017.04.017. 4. ASTM B117-09, Standard Practice for Operating Salt Spray (Fog) Apparatus. 5. K.E. Akoda, et al.: “Impact of Temperature on the Corrosion of Leadfree Solder Alloy during Salt Spray Test,” Microelectron. Reliab., 2021, 126, doi.org/10.1016/j.microrel.2021.114286. 6. K.E. Akoda, et al.: “Dynamics of the Corrosion for SAC305 Solder Alloy in Salt Environment,” 23rd International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2022, doi. org/10.1109/EuroSimE54907.2022.9758896. 7. K.E. Akoda, et al.: “Dynamics of Corrosion on Mechanical and Electrical Reliability of SAC305 Solder Joints during Salt Spray Test,” Microelectron. Reliab., 2023, 150, doi.org/10.1016/ j.microrel.2023.115194. 8. United States Department of Defense. “Department of Defense Test Method Standard: Microcircuits,” MIL-STD-883F, 2010. 9. K. Yokoyama, D. Tsuji, and J. Sakai: “Fracture of Sustained Tensileloaded Sn–3.0Ag–0.5Cu Solder Alloy in NaCl Solution,” Corrosion Science, 2011, 53(10), p. 3331-3336. ABOUT THE AUTHORS Alexandrine Guédon-Gracia is an associate professor at the University of Bordeaux, affiliated with the IMS (Institute of Microelectronics, Microelectronics, and Nanotechnology) laboratory. She is a member of the reliability research group. Her research focuses on analyzing and improving the reliability of electronic assemblies, particularly lead-free solder joints. Komlan Elom Akoda obtained his Ph.D. in 2023 at the University of Bordeaux. Now, he works as material engineer in Akkodis Digital SAS, EDF. Hélène Frémont is a professor at the University of Bordeaux, specializing in microelectronics and the reliability of electronic components. Her research focuses on 3D integration, hybrid bonding, solder material aging, and moisture diffusion in materials. She has supervised 21 doctoral theses and authored over 200 scientific publications. J.Y. Delétage graduated from the University of Bordeaux, France, in 1995 and joined the IXL microelectronic laboratory of this University to work on microassemblies reliability research. He obtained his Ph.D. in 2003. Delétage works now in the IMS laboratory as a research engineer in the reliability group. He runs the experimental platform and aging test resources of the lab. Advertise in Electronic Device Failure Analysis magazine! For information about advertising in Electronic Device Failure Analysis: KJ Johanns, Business Development Manager 440.671.3851, kj.johanns@asminternational.org Current rate card may be viewed online at asminternational.org/advertise.
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 2 24 The 7th annual IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) was held in Huntsville, Alabama, at the Marriott Space and Rocket Center on November 11-13. The conference was loaded with three full days of presentations from industry leaders and sharp technical content focused on microelectronics security and supply chain challenges. This year, the 220 registered attendees represented a ten percent increase year over year and now includes 17 conference sponsors. Day 1 of the conference had a strong focus on packaging technology and assurance with Keynote speakers Jan Vardaman of TechSearch International Inc. and Jeff Krieg from the National Security Agency. An additional highlight was the panel discussion on Advanced Packaging Technology Challenges for Assurance featuring Carl McCants from DARPA, Len Orlando from Ansys Government Initiatives, Anthony Hill from Texas Instruments, Brandon Hamilton from BAE Systems, and Christopher Bailey from Arizona State University. Day 2 emphasized the importance of the U.S. CHIPS Act with a Keynote from George Orji on CHIPS for America: An Up- date on the National Advanced Packaging Manufacturing Program and a full line-up of presentations from NIST researchers, panel discussions, and CHIPS Metrology Rapid Talks. Day 3 led off with Keynote talks from Pauline Paki from the Department of Homeland Security and Chee Lip Gan of Nanyang Technological University and included a range of technical presentations covering side channel attacks, secure microelectronic tracking, and workforce development. The 2024 PAINE Best Paper was awarded to Kevin Pintong and Douglas Summerville for the presentation “Towards Reducing Costs of Side Channel Analysis for Real-time Algorithm Detection.” The best poster award went to Jon Scholl and coauthors at Batelle/AFRL for their work titled “Applying a Trusted Microelectronics Post-silicon Verification and Validation Workflow to Legacy Integrated Circuit Design Recovery.” PAINE also includes a University Lab Virtual Tour Competition with the opportunity to highlight different laboratories facilities and capabilities with the 2024 winning lab from University of Florida – Security and Assurance (SCAN) lab taking the top spot. The 8th annual meeting will be held on October 14–16 in Denver. For more information, visit paine-conference.org. 7TH IEEE INTERNATIONAL CONFERENCE ON PHYSICAL ASSURANCE AND INSPECTION OF ELECTRONICS (PAINE) Michael DiBattista, Varioscale Inc. miked@varioscale.com PAINE CONFERENCE SUMMARY Advertise in Electronic Device Failure Analysis magazine! For information about advertising in Electronic Device Failure Analysis: KJ Johanns, Business Development Manager 440.671.3851, kj.johanns@asminternational.org Current rate card may be viewed online at asminternational.org/advertise.
www.asminternational.orgRkJQdWJsaXNoZXIy MTYyMzk3NQ==