edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 6 particularly those at 10 nm and smaller, require innovative and precise delayering techniques. Argon ion milling from the substrate side using water-assisted etching can achieve nanometer uniformity over the full chip and use UV spectroscopy techniques to determine when to stop on the via or metal interconnect layer. Interconnect layers constructed of copper or aluminum can be analyzed, as well as memory and logic locations. In-chip features designed to store electron charge delayer at an even slower rate as shown, but the authors believe the next steps of involving an electron flood gun will mitigate the positive charge accumulation and allow the sputter rate to normalize across those features. ACKNOWLEDGMENTS Substantial amounts of this work rely on research performed during the Intelligence Advanced Research Project Agency (IARPA) funded project for the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). This project focused on the full analysis of 10 nm integrated circuits using a newly developed scanning argon ion tool, a ZEISS mSEM, and custom developed software for image acquisition and stitching. REFERENCES 1. N. Kovač: “Homogenous Delayering: A Key Challenge for Successful Reverse Engineering,” Fraunhofer Research Institute for Microsystems and Solid State Technologies EMFT, HARRIS Workshop @ Bochum, January 24-25, 2023. 2. A.G. Kimura, et al.: “Applied Failure Analysis Tools and Techniques Toward Integrated Circuit Trust and Assurance,” EDFA, February 2021, 23(1), p. 12-18, doi.org/10.31399/asm.edfa.2021-1.p012. 3. D. Douglass and K. Godin: “Whole-Chip Delayering for Failure Analysis and Quality Assurance,” EDFA, May 2023, 25(2), p. 4-8, doi. org/10.31399/asm.edfa.2023-2.p004. 4. P. Nowakowski, et al.: “An Innovative Technique for Large-scale Delayering of Semiconductor Devices with Nanometric-scale Surface Flatness,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2022, doi. org/10.31399/asm.cp.istfa2022p0414. 5. N. Antoniou and B. Foran: “The EDFAS FA Technology Roadmap—FA Future Roadmap,” EDFA, May 2023, 25(2), p. 44-46, doi.org/10.31399/ asm.edfa.2023-2.p044. 6. E.L. Principe, et al.: “Steps Toward Automated Deprocessing of Integrated Circuits,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2017, p. 285-298, doi.org/10.31399/asm.cp.istfa2017p0285. 7. L. Li-Lung, H. Gao, and H. Xiao: “Surface Effect on SEM Voltage Contrast and Dopant Contrast,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2009, p. 202-207, doi.org/10.31399/asm.cp.istfa2009p0202. 8. C.C. Tsao, et al.: “Reliability of Ultra Thinning of Flip Chips for Through-silicon Analyses,” Proc. IEEE International Reliability Physics Symposium, 2002, p. 198-204, doi.org/10.1109/RELPHY.2002.996636. 9. D. Xia, et al.: “Enhancement of XeF2-assisted Gallium Ion Beam Etching of Silicon Layer and Endpoint Detection from Backside in Circuit Editing,” J. Vac. Sci. Technol. B, 2015, 33, 06F501, doi. org/10.1116/1.4928744. 10. D. Zhang, et al.: “Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits,” 2019. 11. A.W. Czanderna, C.J. Powell, and T.E. Madey: “Specimen Handling, Preparation, and Treatments in Surface Characterization,” Methods of Surface Characterization, Volume 4, Kluwer Academic/Plenum Publishers, New York 1998. 12. N.H. Tolk, et al.: “Photon Emission from Low-energy Ion and Neutral Bombardment of Solids,” Radiation Effects, 1973, 18(3-4), p. 221-229, doi.org/10.1080/00337577308232126. Fig. 8 The corresponding zoomed Metal 2 (M2) layer in the memory block showing cleaning exposed metal interconnects with contrast differences on individual signal lines. Fig. 9 A high resolution multiSEM capture from the logic area showing V0 structures and remnants of the FinFET gates in the decoupling capacitors of the chip. ABOUT THE AUTHORS Michael DiBattista is the vice president at Varioscale Inc. He is currently focused on large scale de- processing on advanced node semiconductor devices and laser and chemical-based solutions for 3D heterogeneous integrated microsystem failure analysis. He has worked in the semiconductor industry for 24 years, holding positions at Intel Corp., FEI Company (ThermoFisher), and Qualcomm Inc. focused on developing tools and technology to support semiconductor physical failure analysis and focused ion beam-based circuit modification. DiBattista has more than 30 publications in the semiconductor, electron/ion microscopy, and chemical sensor fields and has 12 issued patents. He received his Ph.D., M.S.E., and B.S.E. in chemical engineering from the University of Michigan.
RkJQdWJsaXNoZXIy MTYyMzk3NQ==