edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 mSEM and custom capture software. The low magnification stitched image of the high-level structure of blocks shows a large memory location with surrounding logic transistors. Zooming further into the memory block section, the individual tungsten structures are clearly observed in Fig. 6. The memory locations are useful benchmarks for Fig. 5 A stitched scanning electron microscope (SEM) image of the chemically deprocessed integrated circuit at the Metal 0 (M0) layer. The field of view is approximately 64 μm x 50 μm. Fig. 6 A zoomed image of the tungsten M0 layer in the memory block of the 10 nm device. The resolution of the ZEISS mSEM is sufficient to resolve the individual features of the tungsten vias in the memory cells. Fig. 7 A corresponding zoomed image of the copper Via 0 (V0) and the copper Metal 1 (M1) layer that lie under the M0 layer after removal with chemically assisted argon ion sputtering. The image quality allows for stitching and stacking of the layers. the delayering quality because the architecture of the unit cell is easily determined. The mSEM image quality and resolution is challenged with the feature size of 10 nm devices, but it is sufficient to clearly make out individual vias and spacing. Subsequent delayering to the next layer with water assistance and endpointing with UV spectroscopy allows the acquisition of the Via 0 (V0) and Metal 1 (M1) image layer as shown in Fig. 7. The copper M1 horizontal lines and the copper vias are clearly seen. These features are sufficiently delineated such that they can be stacked with the previous M0 layer to begin the layout reconstruction process. After the M1 layer, the process can be repeated through the interconnect stack. Figure 8 shows the Metal 2 layer in the same memory location. The metal interconnect lines are intact but do show contrast differences across the lines that make algorithm-based structure extraction difficult if not impossible.[14] Artificial intelligence-based methods have shown to have much more promise in the initial attempts in the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program. DISCUSSION Chemically assisted scanning Ar+ beam delayering with UV photon-based endpoint detection is a highly successfully method to physically delayer 10 nm ICs across the full chip and areas across the device that delayer slower than their surroundings are observed. This is often due to the circuit architecture. For example, in the logic area, design features like decoupling capacitors are meant to store electrical charge and have demonstrated different sputter rates. This results in remaining material from the layer above while the surrounding areas are cleanly removed as shown in Fig. 9. To remedy this situation in the future, we have incorporated an electron flood gun to balance the accumulated charge in these structures. Delivering a flood of electrons creates an equal potential charge surface that will enable these device structures to interact with the 5 KeV ion beam the same as their surroundings. CONCLUSION Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The challenges associated with advanced node devices,
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