edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 46 The EDFAS Education Subcommittee strives for the development and delivery of educational products to the EDFAS membership. Keeping with its strategic focus on reaching a broader audience, including facilitating Q&A and educational exchanges on the ASM Connect platform, the Subcommittee presents short format videos on selected FA topics. These presentations are available on ASM Connect in the EDFAS online community. Use the following link: https://bit.ly/49Jsg2c. An ASM Connect login is required. EDUCATION NEWS Navid Asadi nasadi@ufl.edu SPOTLIGHT ON TUTORIALS For this issue, we are highlighting a tutorial on failure analysis procedures by Christopher L. Henderson from Semitracks Inc. Failure analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller, and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines to effectively perform failure analysis. This requires knowledge of subjects like design, testing, technology, processing, materials science, chemistry, and even optics. By focusing on a “Do It Right the First Time” approach to the analysis in this tutorial, viewers will learn the appropriate methodology to successfully locate defects, characterize them, and determine the root cause of failure. Learning to recognize correct philosophical principles can lead to a successful analysis. This includes concepts like destructive vs. nondestructive techniques, fast techniques vs. brute force techniques, and correct verification. Chris Henderson is one of the founders and President of Semitracks Inc., which provides training for the semiconductor industry, its customers, and its supply chain. In addition to managing the company, he regularly teaches courses on semiconductor technology and manufacturing, product engineering, reliability, and failure analysis. For additional information on the EDFAS Education Subcommittee, contact Navid Asadi at nasadi@ufl.edu. Fig. 1 Flowchart for package characterization techniques. Fig. 2 Top-level view of a failure analysis process flow for packaged ICs.
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