edfas.org 39 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 The session ended with Jim Colvin, FA Instruments, advocating for a mixed-method approach to address complex prep challenges, likening the use of CNC-based tools to “micro-surgery” with careful materials selection and component stress management. He and other speakers encouraged continued innovation in sample prep, emphasizing the potential for AI and machine learning to enhance precision and repeatability. Overall, this event underscored that while technology is advancing, collaboration and shared expertise remain vital in overcoming challenges and pushing boundaries in sample preparation for microelectronics. We thank the audience and guest speakers for an excellent session and look forward to next year. ISTFA 2024 SYSTEM IN PACKAGE (SIP) USER GROUP Chair/Co-Chairs: Zhiyong Wang, Chandu Tanukonda, and Jer O’Sullivan zhiyong.wang@analog.com, hemachandar.tanukonda.devarajulu@intel.com, jer.osullivan@analog.com The System in Package (SIP) User Group session at ISTFA 2024 brought together industry experts to discuss the pressing challenges and potential solutions in SIP failure analysis (FA). The session began with the chairs identifying critical areas for SIP failure analysis: Design for FA/test, fault isolation (FI), and sample preparation. These areas were highlighted as essential for advancing SIP FA capabilities, which remain challenging despite leveraging existing FA techniques. Jer O’Sullivan, Analog Devices, emphasized the importance of incorporating design for test (DFT) principles, especially in SIPs with diverse analog components. “FA needs to have a seat at the design phase to influence features necessary for downstream FA support,” he stated. Chandu Tanukonda, Intel, echoed this sentiment, highlighting the critical need for design for FA in heterogeneous integration and chiplet-based architectures. “Identifying failing chiplets and ensuring robust test content is more crucial than ever,” he added. Zhiyong Wang initiated a discussion on preferred FI methods in SIPs. Yan Li from Samsung underscored the necessity of nondestructive FI techniques, such as 3D x-ray and lock-in thermography, to accurately locate faults in the X, Y, and Z dimensions of the SIP. “Fault isolation is most troubling for us,” noted Bernice Zee, AMD. Chandu Tanukonda further elaborated on the challenges, stating, “How can we localize the X-Y if it’s too wide? Resolution should be improved.” Some companies are now working on addressing the Z as well. IOs are embedded, how do we access these? A combination of techniques to tackle these challenges is needed, as well as combining both silicon and package expertise. “We should put this in the FA roadmap and collectively clamor for open-source databases,” said Zhiyong Wang and echoed by others. The discussion on sample preparation was led by Zhiyong Wang, who highlighted the challenges in preparing samples for SIP and advanced packaging. Daminda Dahanayaka, IBM, shared experiences using Allied polishers and X-MILL for sample prep, while Tanukonda pointed out the bottlenecks faced with current tools. He suggested that methods like microwave-induced plasma could be promising, albeit with high throughput times. Antonio Tollis from ADI also addressed the complexity of component removal and repackaging as part of the flow for failure validation and isolation. Jer O’Sullivan emphasized the importance of addressing the cost of hardware and related constraints, suggesting that the industry should influence vendors by clearly communicating their pain points. The discussion shifted to the need for establishing design for FA standards in the industry for various SIP architectures. The potential for a separate session on co-packaged optics systems at the next ISTFA was also suggested, given the lack of standardized validation and FI methods in this area. The session concluded with a consensus on the importance of synergetic collaboration between vendors, universities, and FA engineers to address SIP FI-FA challenges. The audience left with a solid understanding of current challenges and future strategies, linking to the SIP FA technology roadmap led by the EDFAS FA technology roadmap councils and CHIPS R&D opportunities. “FA NEEDS TO HAVE A SEAT AT THE DESIGN PHASE TO INFLUENCE FEATURES NECESSARY FOR DOWNSTREAM FA SUPPORT.”
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