edfas.org 3 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 EDFAAO (2025) 1:3-7 1537-0755/$19.00 ©ASM International® FULL CHIP BACKSIDE DELAYERING OF 10 nm NODE INTEGRATED CIRCUITS WITH CHEMICALLY ASSISTED FOCUSED ION BEAM DEPROCESSING Michael DiBattista1, Robert Chivas2, Ata Tafazoli Yazdi1, Jonathan Sheeder1, and Scott Silverman1 1Varioscale, San Marcos, California 2L3Harris, Carlsbad, California miked@varioscale.com INTRODUCTION Physical delayering of semiconductor devices is a critical step for extracting the structure of the internal features used to verify and validate the integrated circuit (IC) design and layout.[1] Delayering techniques allow for the visualization of the lower layers of the IC using microscopy in subsequent steps. This process is essential for security, intellectual property (IP) investigations, and verification and validation activities.[2] The high-level approach is to remove layers of the IC individually, image the device in a scanning electron microscope (SEM), stitch the individual layers together, and then extract information.[3] As the technology manufacturing node has advanced, the corresponding transistor and interconnect layers shrink, resulting in ion-based techniques arising to deal with increased challenges.[4] The features of interest are often too small with too many interconnect layers to be analyzed with optical microscopy or x-ray techniques. Full chip delayering of integrated circuits has been identified as a significant challenge on the Electronic Device Failure Analysis Society (EDFAS) Failure Analysis Roadmap.[5] Advanced manufacturing node devices, particularly those at 10 nm and smaller, present unique challenges due to the nanometer scale of the structures and the layer thickness. BACKGROUND A successful method for large scale full chip delayering of 10 nm ICs is to approach the task from the substrate side of the device.[6] In addition to enabling the visualization of the transistor structure very early in the deprocessing work flow, this also enables examination of the n-well dopant layers with SEM voltage contrast (VC) before the interconnect delayering process starts.[7] Identifying the locations of the n-well and p-well dopant positions helps to distinguish the transistor type and the power (Vdd/Vcc) and ground (GND) interconnect signals that lie deeper in the chip. The substrate side approach also provides significant advantages at 10 nm; the interconnect layers are extremely thin and uniform, reducing some of the more challenging aspects and required time for ion beam milling with chemistry. The process for advanced node delayering begins with precision mechanical thinning of the silicon substrate to below 5 microns of remaining silicon thickness (RST).[8] After the device substrate is thinned, SEM VC inspection is followed by rapid substrate removal with xenon difluoride (XeF2) to the shallow trench isolation (STI) layer. The XeF2 process will stop elegantly on the shallow trench isolation, but the active FinFET transistors will be etched away leaving remaining STI structures intact.[9] This work, featured in this article, takes advantage of chemically assisted argon ion focused ion beam (FIB) processing with ultraviolet (UV) spectroscopy endpointing to destructively delayer starting from the STI layer. This enables follow-on high-resolution SEM imaging at Fig. 1 A chamber view of the argon ion sputtering system, showing the optical view port for UV photon collection, the argon ion source, the gas dosing effuser, and the stage for sample positioning.
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