edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 22 of the Bz field. Due to the broader distribution of the Bz field, spatial resolution is less precise when using Bz for localizing sources. In contrast, the Bx field shows a sharper transition, with a steeper slope around the wire, making it more sensitive to small changes in position. This leads to better spatial resolution, allowing for more accurate identification of the wire’s position and the distance over which the field changes. Thus, for identifying current-carrying features or mapping magnetic fields over small areas, the Bx profiles offer a significant advantage over Bz, which tends to blur finer spatial details due to its broad lateral extensions. This makes the QDM particularly advantageous in such applications, especially for higher stand-off distances where spatial broadening can become critical. Finally, it is important to note that the thickness of the sensor plays a role. Therefore, different diamonds with different properties can be designed for specific use cases, such as die-level or package-level analysis. Further careful system design and calibration can push these boundaries, allowing for more detailed and accurate mapping of magnetic fields in semiconductor devices. CURRENT PATH MAPPING IN NAND GATES NAND gates are a fundamental building block of digital logic in CMOS technology. This section investigates the current paths in the Texas Instruments CD4011B, a quad NAND gate IC shown in Fig. 4 with a publicly available layout. Table 2 presents the truth table for a NAND gate. A logical ‘0’ corresponds to a low voltage relative to ground, while a logical ‘1’ indicates a high voltage. A consistent high state of 5 V was applied to the gate inputs, with the output connected to ground through a 10 kΩ resistor. Each NAND gate comprises two input pins and one output pin. Contact Pins 1 and 2 function as the inputs for the first NAND gate, with Contact Pin 3 serving as the output. This configuration is repeated for the other three NAND gates. Pin 7 is grounded, while Pin 14 serves as the voltage supply (VDD). Magnetic field signatures generated by operating currents under various input configurations were measured using the QDM. Figure 5 illustrates the resulting magnetic fields obtained with a supply current of 8 mA and all input gates set to ‘0’ (i.e., in a low state). The magnetic field maps already contain all the necessary information to localize failures or track current, however, they can be challenging to interpret for the FA engineer, especially for complex chip configurations. To this end, current reconstruction procedures enable reconstructing the current density.[16-18] Using machine learning approaches, allows retrieving the current density path using the magnetic field maps as input data. Figure 6 shows current densities for two distinct gate configurations. Demonstrating the ability to image currents with different gate configurations, establishes the capability to track current paths through ICs. This functionality enables FA engineers to precisely locate areas of anomalous behavior, such as leakage currents, shorts, or open circuits, which are often challenging to detect using traditional methods. Thus, visualizing current flow allows engineers to better understand the nature and location of faults, resulting in more accurate diagnosis and efficient problem-solving. Fig. 4 (a) Layout and (b) infrared image of the Texas Instruments CD4011B IC with four NAND gates. (c) Cross section illustrating the stand-off distance between the sample to probe and the diamond sensor. Table 2 Truth table for a NAND gate, where A and B represent the inputs, and the third column is the resulting output. (a) (b) (c) A B NAND (A, B) 0 0 1 0 1 1 1 0 1 1 1 0
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