edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 10 drain current polarization of 1 µA is shown in Fig. 3. The evolution of the GR noise parameters with the temperature allows construction of Arrhenius plots (as shown in Figs. 4a and 5a) and an estimation from the slope of the evolution of ln(τ0T2) versus 1 ⁄ (k BT ) of the energy difference between the appropriate band energy and the trap energy (ΔE) and from the intercept of this evolution the free carrier capture cross section of the trap. In linear operation, the Lorentzian plateau S0 of the GR noise resulting from traps situated in the depletion region of the transistor may be expressed as:[10-12] (Eq 5) where q is the absolute electron charge, W and L are the effective channel width and length, Cox is the gate capacitance per unit of area, Neff is the surface trap density, NT is the volume trap density, Wd is the silicon depletion depth, and B is a coefficient estimated to be equal to 1/3.[10] As the nanoscaled devices are fully depleted, the silicon depletion depth Wd is taken as half of the fin width (Wfin/2) for FinFET devices, as the Si film thickness (TSi ) for UTBOXs and as half of the nanowire width (WNW/2) for GAA NW FETs. The volume trap density may also be estimated employing the following expression:[10] (Eq 6) However, disagreement between the obtained values of the volume trap densities using Equations 5 and 6 was described in reference 24. This may be related to the theoretical value of the B coefficient, which is evaluated for planar devices with one gate, and to the Wd value as it comes from geometrical consideration as the devices are already fully depleted. It may be suggested that the methods used to estimate the volume trap densities are no longer accurate. Consequently, even if the traps situated in the depletion region are related to a volume phenomenon, as the linear evolution between the plateau and the characteristic frequency of the GR noise contribution gives without any additional assumption the value of the surface trap density, the latter one should be used as a figure of merit when comparing different technologies and architectures. Equation 5 clearly indicates that a linear dependency between the plateau S0 and the characteristic relaxation time constant τ0 of the GR noise should exist. As a consequence, Fig. 2 Example of estimated relaxation time constant of GR contributions as a function of the applied gate voltage (VGS) at 300 K. Device: n channel GAA NW FET, EOT of 5.6 nm, LG / WG = 250 nm / 160 nm, VDS = 50 mV, T = 300 K.[18] The β coefficient of the exponential behavior of the τ 0 with the applied gate voltage (τ0~eβV GS) may give indication of the trap location: for the circle symbols β of -32 V-1 suggests that the traps are located at the Si/dielectric interface;[10] for the triangle and diamond symbols β of -3.5 V-1 and of -3.7 V-1 suggests traps located in the depleted Si film near the Si/dielectric interface,[10,12] and for the square symbols as β of 0 V-1 the traps are located in the depleted Si film.[10] Fig. 3 Typical input-referred voltage power spectrum noise multiplied by the frequency as a function of temperature for the same devices as in Fig. 1.
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